Proposal of a Digital Double Relaxation Oscillation SQUID(Special Issue on Superconductive Electronics)
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概要
- 論文の詳細を見る
We present a digital double relaxation oscillation SQUID (DROS) with a digital flux-locked-loop (FLL) circuit consisting of an up/down counter and a digital-to-analog (D/A) coverter. The up/down counter was designed using 4 jucntion logic (4JL) gates operated with a 2-phase power system. The D/A converter was designed using an R-2R ladder-type D/A converter. We simulated the dynamic behavior of the digital DROS with a digital FLL circuit combined with the 5-bit ripple up/down counter and the D/A converter. Simulation results show correct flux-locked behavior and a high slew rate of 10^7Φ_0/s for the digital DROS.
- 社団法人電子情報通信学会の論文
- 2001-01-01
著者
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明連 広昭
東北大通研
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明連 広昭
埼玉大
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飯塚 剛
愛媛大学理学部
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Takada S
Saitama University Faculty Of Engineering
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Takada S
Saitama Univ. Urawa‐shi Jpn
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Iizuka Tomoya
Graduate School Of Science Osaka University
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Inoue T
Kyokugen Osaka University:crest Japan Science Technology Corporation (jst)
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MYOREN Hiroaki
The authors are with the Faculty of Engineering, Saitama University
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NAKAMURA Mitsunori
The authors are with the Faculty of Engineering, Saitama University
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IIZUKA Takeshi
The authors are with the Faculty of Engineering, Saitama University
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TAKADA Susumu
The authors are with the Faculty of Engineering, Saitama University
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Nakamura Mitsunori
The Authors Are With The Faculty Of Engineering Saitama University
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