A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells(Computer Components)

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概要

• 論文の詳細を見る

• This paper describes the design and development of a module generator for a dual-rail PLA with embedded 2-input logic cells for 0.35μm CMOS technology. In order to automatically generate logic-cell based PLA layouts from circuit specifications, a module generator as a design automation tool of logic-cell based PLA is developed with a structural improvement. This module generator is based on a timing-driven design methodology and consists of logic synthesis, transistor sizing and logic cell generation, stimulus generation, HDL model generation parts. This generator uses a design constraint to achieve a flexible transistor sizing in a logic cell generation part. In addition, generated logic cells can be easily adapted to a layout generator. The layout is generated by using 0.35μm, 3-metal-layer CMOS technology. Moreover, an HDL model generator is developed to create delay behavior models easily and quickly with precise timing parameters. The design complexity which is becoming an important issue for VLSI circuits can be reduced partially and human caused errors are minimized by module generator. A PLA layout in GDS-II form and an HDL model behavior of a Boolean function which has 64-bit input, 1-bit output and 220 product term can be generated within 8 minutes on a SunUltraSPARC-III 900 MHz processor. A very short time is required to compile the module, and this makes it feasible for designers to try many different design configurations in order to get the better one.

• 社団法人電子情報通信学会の論文
• 2005-06-01

著者

• Ikeda Makoto

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Ikeda Makoto

  The Vlsi Design And Education Center The University Of Tokyo

• Ikeda M

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Ikeda Makoto

  Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo

• Ikeda Makoto

  Department Of Agricultural Chemistry Tohoku University:(present)section Of Phytochemical Research Ei

• Asada K

  Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo

• Asada K

  Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T

• Asada Kunihiro

  Department Of Electronic Engineering School Of Engineering The University Of Tokyo:vlsi Design And E

• Yamaoka Hiroaki

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Ikeda M

  Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo

• Asada K

  Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo

• Asada Kunihiro

  Department Of Electrical And Electronic Engineering Tokyo University

• Yoshida Hiroaki

  Department of Cardiology, Himeji Cardiovascular Center

• EKINCIEL Ulkuhan

  Department of Electonics Engineering, Graduate School of Engineering, The University of Tokyo

• YAMAOKA Hiroaki

  Department of Electonics Engineering, Graduate School of Engineering, The University of Tokyo

• Asada K

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• YOSHIDA Hiroaki

  Faculty of Engineering, and VLSI Design and Education Center (VDEC), the University of Tokyo

• Yoshida Hiroaki

  Department Of Cardiology Himeji Cardiovascular Center

• Yoshida H

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Ekinciel Ulkuhan

  Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo

• Yoshida Hiroaki

  Department Of Applied Chemistry Graduate School Of Engineering Osaka University

• Yoshida Hiroaki

  Department Of Aeronautics And Astronautics Graduate School Of Engineering Kyoto University

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