A Low Power and High Throughput Self Synchronous FPGA Using 65nm CMOS with Throughput Optimization by Pipeline Alignment

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概要

• 論文の詳細を見る
• 2010-07-01

著者

• NAKURA Toru

  VLSI Design and Education Center (VDEC), The University of Tokyo

• Ikeda Makoto

  Dept. of Electrical Engineering and Information Systems

• Asada Kunihiro

  Dept. of Electrical Engineering and Information Systems

• Nakura Toru

  Univ. Tokyo Tokyo Jpn

• Ikeda Makoto

  The Vlsi Design And Education Center The University Of Tokyo

• Ikeda Makoto

  Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo

• Asada K

  Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo

• Asada K

  Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T

• Ikeda M

  Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo

• Asada K

  Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo

• Nakura Toru

  Vlsi Design And Education Center (vdec) The University Of Tokyo

• STEFAN DEVLIN

  Dept. of Electrical Engineering and Information Systems, The University of Tokyo

• Stefan Devlin

  Dept. Of Electrical Engineering And Information Systems The University Of Tokyo

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