A Structural Approach for Transistor Circuit Synthesis(Circuit Synthesis,<Special Section>VLSI Design and CAD Algorithms)

スポンサーリンク

概要

• 論文の詳細を見る

• This paper presents a structural approach for synthesizing arbitrary multi-output multi-stage static CMOS circuits at the transistor level, targeting the reduction of transistor counts. To make the problem tractable, the solution space is restricted to the circuit structures which can be obtained by performing algebraic transformations on an arbitrary prime-and-irredundant two-level circuit. The proposed algorithm is guaranteed to find the optimal solution within the solution space. The circuit structures are implicitly enumerated via structural transformations on a single graph structure, then a dynamic-programming based algorithm efficiently finds the minimum solution among them. Experimental results on a benchmark suite targeting standard cell implementations demonstrate the feasibility and effectiveness of the proposed approach. We also demonstrated the efficiency of the proposed algorithm by a numerical analysis on randomly-generated problems.

• 社団法人電子情報通信学会の論文
• 2006-12-01

著者

• Ikeda Makoto

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Ikeda Makoto

  The Vlsi Design And Education Center The University Of Tokyo

• Ikeda Makoto

  Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo

• Asada K

  Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo

• Asada K

  Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T

• Asada Kunihiro

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Yamaoka Hiroaki

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Ikeda M

  Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo

• Asada K

  Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo

• Asada K

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• YOSHIDA Hiroaki

  Faculty of Engineering, and VLSI Design and Education Center (VDEC), the University of Tokyo

• Yoshida H

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Yoshida Hiroaki

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

関連論文

• Time Difference Amplifier with Robust Gain Using Closed-Loop Control
• Data Bypassing Register File for Low Power Microprocessor
• Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme in SOI Technology
• C-12-67 Digital Substrate Noise Canceling Method using Active Guard Ring
• Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability
• Autonomous di/dt Control of Power Supply for Margin Aware Operation(Electronic Circuits)
• Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
• Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs(Papers Selected from AP-ASIC 2004)
• On-Chip di/dt Detector Circuit(Microelectronic Test Structures)
• Stub vs. Capacitor for Power Supply Noise Reduction(Electronic Circuits)
• Noise Immunity Investigation of Low Power Design Schemes(Electronic Circuits)
• On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
• C-12-18 On-chip Detector for Non-Periodic High-Swing Noise Sensing
• A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells(Computer Components)
• A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits(Integrated Electronics)
• A Logic-Cell-Embedded PLA (LCPLA) : An Area-Efficient Dual-Rail Array Logic Architecture(Integrated Electronics)
• Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
• Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
• A-3-7 A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells
• A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers
• SiN_x:H/SiO_2 Double-Layer Passivation With Hydrogen-Radical Annealing For Solar Cells
• Device Parameter Estimation of SOI MOSFET Using One-Dimensional Numerical Simulation Considering Quantum Mechanical Effects
• A Structural Approach for Transistor Circuit Synthesis(Circuit Synthesis,VLSI Design and CAD Algorithms)
• Pixel-Level Color Demodulation Image Sensor for Support of Image Recognition(Electronic Circuits)
• Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories(New System Paradigms for Integrated Electronics)
• A Row-Parallel Position Detector for High-Speed 3-D Camera Based on Light-Section Method(Electronic Circuits)
• High-Sensitivity and Wide-Dynamic-Range Position Sensor Using Logarithmic-Response and Correlation Circuit
• Wide Dynamic Range Photo Detector for Smart Position Sensor Using Log-Response and Correlation Circuit
• An Image Scanning Method with Selective Activation of Tree Structure (Special Issue on New Concept Device and Novel Architecture LSIs)
• A Synchronous Completion Prediction Adder (SCPA)
• Ultimate Lower Bound of Power for MOS Integrated Circuits and Their Applications
• Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells(Circuit Synthesis, VLSI Design and CAD Algorithms)
• Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization(VLSI Design Technology and CAD)
• High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability(Physical Design)(VLSI Design and CAD Algorithms)
• A Low Power and High Throughput Self Synchronous FPGA Using 65nm CMOS with Throughput Optimization by Pipeline Alignment
• A Possible Manipulation of a Biological Cell by a Laser Beam Focused through Optical Fiber
• Experimental Analysis of Optical Trapping System Using Tapered Hemispherically Lensed Optical Fiber
• A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability
• Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method
• A Quantum Algorithm for Searching Web Communities
• -1/5 Power Law in PN-Junction Failure Mechanism Caused by Electrical-Over-Stress
• Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors
• Modeling of Leak Current Characteristics in High Frequency Operation of CMOS Circuits Fabricated on SOI Substrate (Special Issue on Microelectronic Test Structure)
• A New Proposal for Inverter Delay Improvement on CMOS/SOI Future Technology
• Experimental Design of a 32-bit Fully Asynchronous Microprocessor (FAM)
• Numerical Analysis of Durable Power MOSFET Using Cylindrical Device Simulator (Special Section on High-Performance MOS Analog Circuits)
• Effect of Boron on Solid Phase Epitaxy of Ge on Si(111) Surface
• AN ACCIDENT-ANALYSIS OF FINGER AMPUTATION USING 3D FINITE ELEMENT MODEL(3E2 Sports & Impact Biomechanics II)
• P-44 A STUDY OF MATERIAL AND FRICTIONAL PROPERTIES OF THE HUMAN FINGERTIP TO SIMULATE KINETIC FRICTION USING 3D FINITE ELEMENT MODEL
• Test Structure for Characterizing Capacitance Matrix of Multi-Layer Interconnects in VLSI (Special Issue on Microelectronic Test Structures)
• On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
• Cascaded Time Difference Amplifier with Differential Logic Delay Cell
• All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
• 1.0ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells
• Semimicroscopic Study on Inelastic Behavior of Polycrystalline Metal under Varying-Temperature Conditions
• On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction
• Thermal condensation in solid state of N-hydroxyalkyl-2-imidazolidinone.

もっと見る 閉じる

スポンサーリンク