A New Proposal for Inverter Delay Improvement on CMOS/SOI Future Technology
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概要
- 論文の詳細を見る
High performances of CMOS / SOI inverter by simulations of analytical model, reducing the poly-Si gate thickness (t_m), and experiments are verified and proposed. It is shown that the t_m and gate oxide thickness (t_<ox>) are correlated to gate fringing capacitance, which largely influences on the Propagation Delay Time (TPD) [7]. Contributions of gate fringing capacitance to CMOS / SIMOX inverter time delay in deep submicrometer gate devices are propounded. Measurements of the fifty-one stage ring oscillator's TPDs are completed for comparison with analytical model [7]. Simulation results by the analytical model, including Time-Dependent Gate Capacitance (TDGC) model, agree well with the experimental results at the same conditions. Simulation results are also predicted that SOI technology is promising for speed enhancement by reducing the poly-Si gate thickness, while the t_<ox> remains constant. It is concluded that the TPDs by reducing the t_m to zero are improved up to about two times faster than typically fabricated ring oscillator at 350nm of the t_m in deep-submicrometer gate CMOS / SIMOX inverters at room temperature.
- 社団法人電子情報通信学会の論文
- 1993-10-25
著者
-
Asada Kunihiro
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
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Lee M.O.
Faculty of Engineering, The University of Tokyo
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Lee M.o.
Faculty Of Engineering The University Of Tokyo:nippon Motorola Ltd.
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