-1/5 Power Law in PN-Junction Failure Mechanism Caused by Electrical-Over-Stress

スポンサーリンク

概要

• 論文の詳細を見る
• 1992-02-25

著者

• Asada Kunihiro

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Tajima Yutaka

  Faculty Of Engineering The University Of Tokyo

• Asada Kunihiro

  Faculty Of Engineering The University Of Tokyo

• SUGANO Takuo

  Faculty of Engineering, The University of Tokyo

• Sugano Takuo

  Faculty Of Engineering The University Of Tokyo

関連論文

• Data Bypassing Register File for Low Power Microprocessor
• Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability
• A Structural Approach for Transistor Circuit Synthesis(Circuit Synthesis,VLSI Design and CAD Algorithms)
• Pixel-Level Color Demodulation Image Sensor for Support of Image Recognition(Electronic Circuits)
• Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories(New System Paradigms for Integrated Electronics)
• A Row-Parallel Position Detector for High-Speed 3-D Camera Based on Light-Section Method(Electronic Circuits)
• High-Sensitivity and Wide-Dynamic-Range Position Sensor Using Logarithmic-Response and Correlation Circuit
• Wide Dynamic Range Photo Detector for Smart Position Sensor Using Log-Response and Correlation Circuit
• A Synchronous Completion Prediction Adder (SCPA)
• Ultimate Lower Bound of Power for MOS Integrated Circuits and Their Applications
• A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability
• -1/5 Power Law in PN-Junction Failure Mechanism Caused by Electrical-Over-Stress
• Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors
• Modeling of Leak Current Characteristics in High Frequency Operation of CMOS Circuits Fabricated on SOI Substrate (Special Issue on Microelectronic Test Structure)
• A New Proposal for Inverter Delay Improvement on CMOS/SOI Future Technology
• Experimental Design of a 32-bit Fully Asynchronous Microprocessor (FAM)
• Numerical Analysis of Durable Power MOSFET Using Cylindrical Device Simulator (Special Section on High-Performance MOS Analog Circuits)
• Test Structure for Characterizing Capacitance Matrix of Multi-Layer Interconnects in VLSI (Special Issue on Microelectronic Test Structures)
• Cascaded Time Difference Amplifier with Differential Logic Delay Cell
• 1.0ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells

もっと見る 閉じる

スポンサーリンク