A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability
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概要
- 論文の詳細を見る
Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption reduction by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.
- 社団法人電子情報通信学会の論文
- 1995-04-25
著者
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Akita J
Univ. Tokyo Tokyo Jpn
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Asada Kunihiro
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
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Akita Junichi
Faculty of Engineering, The University of Tokyo
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