Experimental Design of a 32-bit Fully Asynchronous Microprocessor (FAM)
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概要
- 論文の詳細を見る
This paper describes a 32-bit fully asynchronous microprocessor, with 4-stage pipeline based on a RISC-like architecture. Issues relevant to the processor such as design of self-timed datapath, asynchronous controller and interconnection circuits are discussed. Simulation results are included using parameters extracted from layout, which showed about the 300 MIPS processing speed and used 71,000 transistors with .5 μm CMOS technology.
- 社団法人電子情報通信学会の論文
- 1994-04-25
著者
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Asada Kunihiro
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
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Cho Kyoung-rok
Dept. Of Comp. & Commu. Eng. Chungbuk National University
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Okura Kazuma
Faculty of Engineering, The University of Tokyo
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Okura Kazuma
Faculty Of Engineering The University Of Tokyo
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