1.0ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells
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概要
- 論文の詳細を見る
This paper proposes a time-to-digital converter (TDC) utilizing the cascaded time difference amplifier (TDA) and shows measurement results with 0.18µm CMOS. The proposed TDC operates in two modes, a wide input range mode and a fine time resolution mode. We employ a non-linearity calibration technique based on a lookup table. The wide input range mode shows 10.2ps time resolution over 1.3ns input range with DNL and INL of +0.8/-0.7LSB and +0.8/-0.4LSB, respectively. The fine time resolution mode shows 1.0ps time resolution over 60ps input range with DNL and INL of +0.9/-0.9LSB and +0.8/-1.0LSB, respectively.
- 2011-06-01
著者
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Nakura Toru
Univ. Tokyo Tokyo Jpn
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Ikeda Makoto
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
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Ikeda Makoto
The Vlsi Design And Education Center The University Of Tokyo
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Ikeda Makoto
Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo
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Asada K
Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo
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Asada K
Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T
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Asada Kunihiro
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
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MANDAI Shingo
Faculty of Engineering, and VLSI Design and Education Center (VDEC), The University of Tokyo
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Asada K
Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo
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Mandai Shingo
Dept. Of Electronic Engineering The University Of Tokyo
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Nakura Toru
Vlsi Design And Education Center (vdec) The University Of Tokyo
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Iizuka Tetsuya
Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T
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Iizuka Tetsuya
Vlsi Design And Education Center (vdec) The University Of Tokyo
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