Cascaded Time Difference Amplifier with Differential Logic Delay Cell

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概要

• 論文の詳細を見る

• We introduce a 16x cascaded time difference amplifier (TDA) using a differential logic delay cell with 0.18µm CMOS process. By employing the differential logic delay cell in the delay chain instead of the CMOS logic delay cell, less than 8% TD gain offset with ±150ps input range is achieved. The input referred standard deviation of the output time difference error is 2.7ps and the input referred is improved by 17% compared with that of the previous TDA using the CMOS logic delay cell.

• （社）電子情報通信学会の論文
• 2011-04-01

著者

• Nakura Toru

  Univ. Tokyo Tokyo Jpn

• Ikeda Makoto

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Ikeda Makoto

  The Vlsi Design And Education Center The University Of Tokyo

• Ikeda Makoto

  Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo

• Asada K

  Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo

• Asada K

  Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T

• Asada Kunihiro

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• MANDAI Shingo

  Faculty of Engineering, and VLSI Design and Education Center (VDEC), The University of Tokyo

• Asada K

  Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo

• Mandai Shingo

  Dept. Of Electronic Engineering The University Of Tokyo

• Nakura Toru

  Vlsi Design And Education Center (vdec) The University Of Tokyo

• Iizuka Tetsuya

  Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T

• IIZUKA Tetsuya

  VLSI Design and Education Center (VDEC), The University of Tokyo

• Iizuka Tetsuya

  Vlsi Design And Education Center (vdec) The University Of Tokyo

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