All-digital ramp waveform generator for two-step single-slope ADC
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概要
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This paper presents an all-digital on-chip ramp waveform generator for an 8-bit single-slope ADC. The proposed ramp waveform generator consists of static CMOS digital circuits and is designed using standard cells aiming for the process portability. The proposed circuit realizes digitally-controlled ramp output and also realizes two step coarse-fine ramp waveform to speed up the single-slope analog-to-digital conversion. The experimental results of the circuit simulation with random variation on 0.18µm CMOS process demonstrate the feasibility of our ramp waveform generator and 8-bit two-step single-slope ADC with DNL within ±0.2LSB and INL within ±0.8LSB.
著者
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Asada Kunihiro
Vlsi Design And Education Center (vdec) The University Of Tokyo
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Iizuka Tetsuya
Vlsi Design And Education Center (vdec) The University Of Tokyo
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Iizuka Tetsuya
VLSI Design and Education Center (VDEC), University of Tokyo
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