A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-Chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application
スポンサーリンク
概要
- 論文の詳細を見る
- 2011-12-01
著者
-
Asada Kunihiro
Vlsi Design And Education Center (vdec) The University Of Tokyo
-
Asada Kunihiro
The University Of Tokyo
-
Mai Khanh
The University Of Tokyo
-
Sasaki Masahiro
Vlsi Design And Education Center (vdec) The University Of Tokyo
-
MAI KHANH
Graduate School of Engineering, The University of Tokyo
関連論文
- All-digital ramp waveform generator for two-step single-slope ADC
- Time Difference Amplifier with Robust Gain Using Closed-Loop Control
- Approaches for Reducing Power Consumption in VLSI Bus Circuits (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
- Autonomous di/dt Control of Power Supply for Margin Aware Operation(Electronic Circuits)
- Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs(Papers Selected from AP-ASIC 2004)
- On-Chip di/dt Detector Circuit(Microelectronic Test Structures)
- Stub vs. Capacitor for Power Supply Noise Reduction(Electronic Circuits)
- Initial Stage of Stress-Induced Migration Phenomenon in Aluminum Interconnection on Semiconductor Device
- Noise Immunity Investigation of Low Power Design Schemes(Electronic Circuits)
- Device Parameter Estimation of SOI MOSFET Using One-Dimensional Numerical Simulation Considering Quantum Mechanical Effects
- LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil(Physical Design,VLSI Design and CAD Algorithms)
- The Characterization of the Variability of Silicon Wafers by Leakage Current Measurements
- A System Level Optimization Techinique for Application Specific Low Power Memories(Special Section on VLSI Design and CAD Algorithms)
- Design of a Conditional Sign Decision Booth Encoder for a High Performance 32 ★ 32-Bit Digital Multiplier
- A 0.18-μm CMOS X-Band Shock Wave Generator with an On-Chip Dipole Antenna and a Digitally Programmable Delay Circuit for Pulse Beam-Formability
- On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
- All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
- A 0.25-μm Si-Ge Fully Integrated Pulse Transmitter with On-Chip Loop Antenna Array towards Beam-Formability for Millimeter-Wave Active Imaging
- A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-Chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application
- Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter
- On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction
- High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters
- Initial Stage of Stress-Induced Migration Phenomenon in Aluminum Interconnection on Semiconductor Device
- A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing