On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction

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概要

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• Switched parasitic capacitors of sleep blocks with a tri-mode power gating structure are implemented to reduce on-chip resonant supply noise in 1.2V, 65nm standard CMOS process. The tri-mode power gating structure makes it possible to store charge into the parasitic capacitance of the power gated blocks. The proposed method achieves 53.1% and 57.9% noise reduction for wake-up noise and 130MHz periodic supply noise, respectively. It also realizes noise cancelling without discharging time before using parasitic capacitors of sleep blocks, and shows 8.4x boost of the effective capacitance value with 2.1% chip area overhead. The proposed method can save the chip area for reducing resonant supply noise more effectively.

著者

• Asada Kunihiro

  Vlsi Design And Education Center (vdec) The University Of Tokyo

• Ikeda Makoto

  Vlsi Design And Education Center (vdec) The University Of Tokyo

• Nakura Toru

  Vlsi Design And Education Center (vdec) The University Of Tokyo

• Kim Jinmyoung

  Dept. Of Electrical Engineering And Information Systems The University Of Tokyo

• Takata Hidehiro

  Design Platform Dev. Div. Renesas Electronics Corp.

• Ishibashi Koichiro

  Design Platform Dev. Div. Renesas Electronics Corp.

• ISHIBASHI Koichiro

  Design Platform Development Division, Renesas Electronics Corporation

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