D-6-4 Analysis of On-Line Clustering Algorithm for Low-Power Hardware Implementation

スポンサーリンク

概要

• 論文の詳細を見る
• 2012-03-06

著者

• Ikeda Makoto

  Vlsi Design And Education Center (vdec) The University Of Tokyo

• Chen Tse-wei

  Vlsi Design And Education Center The University Of Tokyo

関連論文

• Time Difference Amplifier with Robust Gain Using Closed-Loop Control
• Approaches for Reducing Power Consumption in VLSI Bus Circuits (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
• Autonomous di/dt Control of Power Supply for Margin Aware Operation(Electronic Circuits)
• Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs(Papers Selected from AP-ASIC 2004)
• On-Chip di/dt Detector Circuit(Microelectronic Test Structures)
• Stub vs. Capacitor for Power Supply Noise Reduction(Electronic Circuits)
• Noise Immunity Investigation of Low Power Design Schemes(Electronic Circuits)
• LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil(Physical Design,VLSI Design and CAD Algorithms)
• On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
• All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
• D-6-4 Analysis of On-Line Clustering Algorithm for Low-Power Hardware Implementation
• On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction
• High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters

もっと見る 閉じる

スポンサーリンク