Approaches for Reducing Power Consumption in VLSI Bus Circuits (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
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概要
- 論文の詳細を見る
This paper summarizes power reduction methods applicable for VLSI bus systems in terms of reduction of signal swing, effective capacitance reduction and reduction of signal transition, which have been studied in authors' research group. In each method the basic concept is reviewed quickly along with some examples of its application. A future perspective is also described in conclusion.
- 社団法人電子情報通信学会の論文
- 2000-02-25
著者
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IKEDA Makoto
VLSI Design and Education Center (VDEC), The University of Tokyo
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ASADA Kunihiro
VLSI Design and Education Center (VDEC), The University of Tokyo
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KOMATSU Satoshi
VLSI Design and Education Center (VDEC), The University of Tokyo
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Komatsu S
Univ. Tokyo Tokyo Jpn
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Komatsu Satoshi
Vlsi Design And Education Center (vdec) The University Of Tokyo
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Asada Kunihiro
Vlsi Design And Education Center (vdec) The University Of Tokyo
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Ikeda Makoto
Vlsi Design And Education Center (vdec) The University Of Tokyo
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Ikeda Makoto
Vlsi Design And Education Center The University Of Tokyo
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