Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks(Power Optimization)(<Special Section>VLSI Design and CAD Algorithms)

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概要

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• The power dissipation at the off-chip bus has become a significant part of the overall power dissipation in micro-processor based digital systems. This paper presents irredundant address bus encoding methods which reduce signal transitions on the instruction address buses by using adaptive codebook methods. These methods are based on the temporal locality and spatial locality of instruction address. Since applications tend to JUMP/BRANCH to limited sets of addresses, proposed encoding methods assign the least signal transition codes to the addresses of JUMP/BRANCH operations in the past. In addition, our methods can be easily applicable for conventional digital systems since they are irredundant encoding methods. Our encoding methods reduce the signal transitions on the instruction address buses, which results in the reduction of total power dissipation of digital systems. Experimental results show that our methods can reduce the signal transition by an average of 88%.

• 社団法人電子情報通信学会の論文
• 2003-12-01

著者

• Komatsu Satoshi

  Vlsi Design And Education Center (vdec) The University Of Tokyo

• FUJITA Masahiro

  Faculty of Engineering, University of Tokyo

• Fujita M

  Vlsi Design And Education Center (vdec) The University Of Tokyo

• Fujita Masahiro

  Faculty Of Engineering Kumamoto University

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