Design of a Conditional Sign Decision Booth Encoder for a High Performance 32 ★ 32-Bit Digital Multiplier
スポンサーリンク
概要
- 論文の詳細を見る
In this paper, a high performance 32 ★ 32-bit multiplier for a DSP core is proposed. The multiplier is composed of a block of Booth Encoder, a block of data compression, and a block of a 64-bit adder. In the block of Booth encoder, a conditional sign decision Booth encoder that reduces the gate delay and power consumption is proposed. In the block of data compression, 4-2 and 9-2 data compressors based on a novel compound logic are used for the efficient compressing of extra sign bit. In the block of 64-bit adder, an adaptive MUX-based conditional select adder with a separated carry generation block is proposed. The proposed 32 ★ 32-bit multiplier is designed by a full-custom method and there are about 28,000 transistors in an active area of 900 ★m ★ 500 ★m with 0.25 ★m CMOS technology. From the experimental results, the multiplication time of the multiplier is about 3.2 ns at 2.5 V power supply, and it consumes about 50 mW at 100MHz.
- 社団法人電子情報通信学会の論文
- 2002-09-01
著者
-
ASADA Kunihiro
VLSI Design and Education Center (VDEC), The University of Tokyo
-
Asada Kunihiro
Vlsi Design And Education Center (vdec) The University Of Tokyo
-
Song Minkyu
Department Of Semiconductor Science Dongguk University
関連論文
- Time Difference Amplifier with Robust Gain Using Closed-Loop Control
- All-digital ramp waveform generator for two-step single-slope ADC
- Time Difference Amplifier with Robust Gain Using Closed-Loop Control
- Approaches for Reducing Power Consumption in VLSI Bus Circuits (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
- Autonomous di/dt Control of Power Supply for Margin Aware Operation(Electronic Circuits)
- Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs(Papers Selected from AP-ASIC 2004)
- On-Chip di/dt Detector Circuit(Microelectronic Test Structures)
- Stub vs. Capacitor for Power Supply Noise Reduction(Electronic Circuits)
- Initial Stage of Stress-Induced Migration Phenomenon in Aluminum Interconnection on Semiconductor Device
- Noise Immunity Investigation of Low Power Design Schemes(Electronic Circuits)
- Device Parameter Estimation of SOI MOSFET Using One-Dimensional Numerical Simulation Considering Quantum Mechanical Effects
- LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil(Physical Design,VLSI Design and CAD Algorithms)
- Power Optimization for Data Compressors Based on a Window Detector in a 54 × 54 Bit Multiplier
- A 3V 8-Bit 200MSPS CMOS ADC with an Improved Analog Latch and a Novel Digital Encoder(Special Issue on High-Performance Analog Integrated Circuits)
- A System Level Optimization Techinique for Application Specific Low Power Memories(Special Section on VLSI Design and CAD Algorithms)
- Design of a Conditional Sign Decision Booth Encoder for a High Performance 32 ★ 32-Bit Digital Multiplier
- On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
- All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
- A 0.25-μm Si-Ge Fully Integrated Pulse Transmitter with On-Chip Loop Antenna Array towards Beam-Formability for Millimeter-Wave Active Imaging
- A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-Chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application
- Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter
- On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction
- High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters
- Initial Stage of Stress-Induced Migration Phenomenon in Aluminum Interconnection on Semiconductor Device
- A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing