Komatsu Satoshi | Vlsi Design And Education Center (vdec) The University Of Tokyo

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概要

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著作論文

Synchronization Verification in System-Level Design with ILP Solvers(System Level Design,VLSI Design and CAD Algorithms)
Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications(Low Power Methodology, VLSI Design and CAD Algorithms)
Approaches for Reducing Power Consumption in VLSI Bus Circuits (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
The AMS Extension to System Level Design Language-SpecC(System Level Design,VLSI Design and CAD Algorithms)
Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks
Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks(Power Optimization)(VLSI Design and CAD Algorithms)
Interconnect-Aware Pipeline Synthesis for Array-Based Architectures
Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams(Logic and High Synthesis)(VLSI Design and CAD Algorithms)
High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters
A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing

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