Fujita Masahiro | Vlsi Design And Education Center (vdec) The University Of Tokyo

スポンサーリンク

概要

関連著者

もっと見る

著作論文

Synchronization Verification in System-Level Design with ILP Solvers(System Level Design,VLSI Design and CAD Algorithms)
Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications(Low Power Methodology, VLSI Design and CAD Algorithms)
Reducing scheduling overheads in dynamically reconfigurable processors (VLSI設計技術)
Reducing scheduling overheads in dynamically reconfigurable processors (コンピュータシステム)
Reducing scheduling overheads in dynamically reconfigurable processors (リコンフィギャラブルシステム)
The AMS Extension to System Level Design Language-SpecC(System Level Design,VLSI Design and CAD Algorithms)
Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath
Interconnect-Aware Pipeline Synthesis for Array-Based Architectures
Multi-Level Bounded Model Checking with Symbolic Counterexamples
A Unified Framework for Equivalence Verification of Datapath Oriented Applications
An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences(Simulation and Verification, VLSI Design and CAD Algorithms)
An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging
Transaction Ordering in Network-on-Chips for Post-Silicon Validation

もっと見る

スポンサーリンク