Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications(Low Power Methodology, <Special Section>VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
Energy consumption is one of the most critical constraints in the current VLSI system designs. In addition, fault tolerance of VLSI systems will be also one of the most important requirements in the future shrunk VLSIs. This paper proposes practical low power and fault tolerant bus encoding methods in on-chip data transfer. The proposed encoding methods use the combination of simple low power code and fault tolerant code. Experimental results show that the proposed methods can reduce signal transitions by 23% on the bus with fault tolerance. In addition, circuit implementation results with bus signal swing optimization show the effectiveness of the proposed encoding methods. We show also the selection methodology of the optimum encoding method under the given requirements.
- 社団法人電子情報通信学会の論文
- 2005-12-01
著者
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KOMATSU Satoshi
VLSI Design and Education Center (VDEC), The University of Tokyo
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FUJITA Masahiro
VLSI Design and Education Center (VDEC), The University of Tokyo
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Komatsu Satoshi
Univ. Of Tokyo Tokyo Jpn
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Komatsu Satoshi
Vlsi Design And Education Center (vdec) The University Of Tokyo
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Fujita Masahiro
Vlsi Design And Education Center The University Of Tokyo
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Fujita Masahiro
Vlsi Design And Education Center (vdec) The University Of Tokyo
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