Reducing scheduling overheads in dynamically reconfigurable processors (コンピュータシステム)

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Dynamically reconfigurable computing holds the promise of achieving breakthroughs that significantly enhance systems performance. Often size of a reconfigurable fabric is small when compared to application's dataflow graph. The application is broken down into smaller sub-tasks. These sub-tasks have to be sequenced based on data and control dependences for correct execution. Typically, in most of the dynamically reconfigurable processors, the overheads due to non-execution activities are quite high. The non-execution activities include (1) sequencing of sub-tasks as per data flow order (2) determining their placement on the reconfigurable fabric (3) launching them onto the reconfigurable fabric and (4) performing data exchange between sub-tasks. We use REDEFINE as our target Dynamically Reconfigurable Processor, where application sub-tasks are referred to as hyperops. In REDEFINE, the overheads of non-execution activities viz. sequencing and launching, are reported to be as high as 50% of the overall execution time. The aim of this work is to hide the latencies due to these overheads. This is done by appropriately prefetching the hyperops ahead of time, and thereby improving the overall performance. An interaction graph, which captures the control and data dependences between hyperops, is constructed. We use speculative trace scheduling method to predict the next hyperop to be prefetched. The existing REDEFINE framework is modified to include a prediction unit. Simulation results show around 12-27% reduction in overall execution time, when compared to the execution time without prefetching. This is achieved due to 31-68% reduction in overheads of sequencing and launching.
2010-01-19

Reducing scheduling overheads in dynamically reconfigurable processors (コンピュータシステム)

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