Reducing scheduling overheads in Dynamically Reconfigurable Processors

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概要

• 論文の詳細を見る
• 2010-01-19

著者

• FUJITA Masahiro

  VLSI Design and Education Center (VDEC), The University of Tokyo

• Krishnamoorthy Ratna

  Department Of Electronics Engineering The University Of Tokyo

• Varadarajan Keshavan

  CAD Lab, Supercomputing Education and Research Centre, Indian Institute of Science

• Alle Mythri

  CAD Lab, Supercomputing Education and Research Centre, Indian Institute of Science

• Narayan Ranjani

  Morphing Machines Pvt. Ltd., Entrepreneurship Center, Indian Institute of Science

• Nandy S

  CAD Lab, Supercomputing Education and Research Centre, Indian Institute of Science

• Varadarajan Keshavan

  Cad Lab Supercomputing Education And Research Centre Indian Institute Of Science

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