Transaction Ordering in Network-on-Chips for Post-Silicon Validation

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概要

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• In this paper, we have addressed the problem of ordering transactions in network-on-chips (NoCs) for post-silicon validation. The main idea is to extract the order of the transactions from the local partial orders in each NoC tile based on a set of “happened-before” rules, assuming transactions do not have a timestamp. The assumption is based on the fact that implementation and usage of a global time as timestamp in such systems may not be practical or efficient. When a new transaction is received in a tile, we send special messages to the neighboring tiles to inform them regarding the new transaction. The process of sending those special messages continues recursively in all the tiles that receive them until another such special message is detected. This way, we relate local orders of different tiles with each other. We show that our method can reconstruct the correct transaction orders when communication delays are deterministic. We have shown the effectiveness of our method by correctly ordering the transaction in NoCs with mesh and torus topologies with different sizes from 5*5 to 9*9. Also, we have implemented the proposed method in hardware to show its feasibility.

著者

• Fujita Masahiro

  Vlsi Design And Education Center (vdec) The University Of Tokyo

• Fujita Masahiro

  VLSI Design and Education Center, the University of Tokyo

• GHAREHBAGHI Amir

  VLSI Design and Education Center, The University of Tokyo

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