Initial Stage of Stress-Induced Migration Phenomenon in Aluminum Interconnection on Semiconductor Device
スポンサーリンク
概要
- 論文の詳細を見る
The initial stage of stress-induced migration in aluminum interconnections on semiconductor devices was studied through measurements of the electric resistivity and the residual-stress, as well as observations of grain growth during high temperature storage. It was shown that characteristics of the initial stage varied markedly depending on the storage temperature and period. The variation of the characteristics was affected not only by (1) increase in grain size or decrease in dislocation density upon recrystallization, but also by (2) degeneration at the grain boundary in the aluminum interconnection, which was considered to be a pile-up of dislocations. In this paper, we propose a model that the initial stage of the stress-induced migration is determined by competition between phenomena (1) and (2), and discuss the possibility that the open failure rate of the interconnection is correlated qualitatively with the change in the electrical resistivity at the initial stage.
- INSTITUTE OF PURE AND APPLIED PHYSICSの論文
- 1997-05-15
著者
-
Aoyagi Minoru
School Of Engineering University Of Tokyo:nissan Motor Co. Ltd.
-
Asada Kunihiro
Vlsi Design And Education Center (vdec) The University Of Tokyo
-
Aoyagi Minoru
School of Engineering, University of Tokyo, 3-1 Hongo 7, Bunkyo-ku, Tokyo 113, Japan
関連論文
- All-digital ramp waveform generator for two-step single-slope ADC
- Time Difference Amplifier with Robust Gain Using Closed-Loop Control
- Approaches for Reducing Power Consumption in VLSI Bus Circuits (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
- Autonomous di/dt Control of Power Supply for Margin Aware Operation(Electronic Circuits)
- Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs(Papers Selected from AP-ASIC 2004)
- On-Chip di/dt Detector Circuit(Microelectronic Test Structures)
- Stub vs. Capacitor for Power Supply Noise Reduction(Electronic Circuits)
- Initial Stage of Stress-Induced Migration Phenomenon in Aluminum Interconnection on Semiconductor Device
- Noise Immunity Investigation of Low Power Design Schemes(Electronic Circuits)
- Device Parameter Estimation of SOI MOSFET Using One-Dimensional Numerical Simulation Considering Quantum Mechanical Effects
- LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil(Physical Design,VLSI Design and CAD Algorithms)
- A System Level Optimization Techinique for Application Specific Low Power Memories(Special Section on VLSI Design and CAD Algorithms)
- Design of a Conditional Sign Decision Booth Encoder for a High Performance 32 ★ 32-Bit Digital Multiplier
- On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
- All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
- A 0.25-μm Si-Ge Fully Integrated Pulse Transmitter with On-Chip Loop Antenna Array towards Beam-Formability for Millimeter-Wave Active Imaging
- A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-Chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application
- Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter
- On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction
- High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters
- Initial Stage of Stress-Induced Migration Phenomenon in Aluminum Interconnection on Semiconductor Device
- A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing