A 8bit two stage time-to-digital converter using time difference amplifier
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概要
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We propose a 8bit two stage time-to-digital converter (TDC) using a time difference amplifier. The time resolution is 1.89ps, and DNL of 0.9 and INL of 1.0 are achieved in simulation assuming the standard 0.18um CMOS. To amplify the time residue of the first stage, the 16x cascaded time difference amplifier (TDA) using differential logic delay cells is employed. Time resolution of the proposed TDC becomes finer by employing the 16x cascaded TDA and the linearity is improved by using only one TDA in the two stage TDC instead of using a lot of TDAs.
著者
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NAKURA Toru
VLSI Design and Education Center (VDEC), The University of Tokyo
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MANDAI Shingo
Dept. of Electronic Engineering, The University of Tokyo
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Ikeda Makoto
Dept. of Electrical Engineering and Information Systems
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Asada Kunihiro
Dept. of Electrical Engineering and Information Systems
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Nakura Toru
Vlsi Design And Education Center (vdec) The University Of Tokyo
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Mandai Shingo
Dept. of Electrical Engineering and Information Systems
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