Nakura Toru | Univ. Tokyo Tokyo Jpn
スポンサーリンク
概要
関連著者
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Nakura Toru
Univ. Tokyo Tokyo Jpn
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Ikeda Makoto
The Vlsi Design And Education Center The University Of Tokyo
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Ikeda Makoto
Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo
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Asada K
Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo
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Asada K
Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T
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Asada K
Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo
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Ikeda M
Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo
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Asada Kunihiro
Vlsi Design And Education Center (vdec) The University Of Tokyo
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Ikeda Makoto
Vlsi Design And Education Center (vdec) The University Of Tokyo
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Nakura Toru
Vlsi Design And Education Center (vdec) The University Of Tokyo
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IKEDA Makoto
VLSI Design and Education Center (VDEC), The University of Tokyo
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ASADA Kunihiro
VLSI Design and Education Center (VDEC), The University of Tokyo
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Mandai Shingo
Dept. Of Electronic Engineering The University Of Tokyo
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NAKURA Toru
VLSI Design and Education Center (VDEC), The University of Tokyo
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Nakura Toru
Dept. Of Electronic Engineering The Univ. Of Tokyo
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Ikeda Makoto
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
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Asada Kunihiro
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
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MANDAI Shingo
Faculty of Engineering, and VLSI Design and Education Center (VDEC), The University of Tokyo
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Iizuka Tetsuya
Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T
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Iizuka Tetsuya
Vlsi Design And Education Center (vdec) The University Of Tokyo
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Ikeda Makoto
Dept. of Electrical Engineering and Information Systems
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Asada Kunihiro
Dept. of Electrical Engineering and Information Systems
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IIZUKA Tetsuya
VLSI Design and Education Center (VDEC), The University of Tokyo
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Kim Jinmyoung
Dept. Of Electrical Engineering And Information Systems The University Of Tokyo
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Takata Hidehiro
Design Platform Dev. Div. Renesas Electronics Corp.
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Ishibashi Koichiro
Design Platform Dev. Div. Renesas Electronics Corp.
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Ikeda Makoto
The Vlsi Design And Education Center (vdec) The University Of Tokyo
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Asada Kunihiro
The Vlsi Design And Education Center (vdec) The University Of Tokyo
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ASADA Kunihiro
The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC)
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MANDAI Shingo
Dept. of Electronic Engineering, The University of Tokyo
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Nakura Toru
The Dept. Of Electronic Engineering The Univ. Of Tokyo
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Lan Dang
Dept. Of Engineering University Of Tokyo
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Asada Kunihiro
The Vlsi Design And Education Center The University Of Tokyo
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NAKURA Toru
Faculty of Engineering, and VLSI Design and Education Center (VDEC), The University of Tokyo
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NAKURA Toru
Department of Electronic Engineering, The University of Tokyo
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STEFAN DEVLIN
Dept. of Electrical Engineering and Information Systems, The University of Tokyo
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Stefan Devlin
Dept. Of Electrical Engineering And Information Systems The University Of Tokyo
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Ishibashi Koichiro
Design Platform Development Division Renesas Electronics Corporation
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KIM Jinmyoung
Dept. of Electrical Engineering and Information Systems, The University of Tokyo
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TAKATA Hidehiro
Design Platform Development Division, Renesas Electronics Corporation
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JEONG Jaehyun
Department of Electrical Engineering and Information Systems, The University of Tokyo
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Jeong Jaehyun
Department Of Electrical Engineering And Information Systems The University Of Tokyo
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Takata Hidehiro
Design Platform Development Division Renesas Electronics Corporation
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Nakura Toru
The Vlsi Design And Education Center (vdec) The University Of Tokyo
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KIM Jinmyoung
the Dept. of Electrical Engineering and Information Systems, The University of Tokyo
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Mandai Shingo
Dept. of Electrical Engineering and Information Systems
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NAKURA Toru
Department of Electrical Engineering and Information Systems, The University of Tokyo
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NAKURA Toru
the Department of Electrical Engineering and Information Systems, The University of Tokyo
著作論文
- Time Difference Amplifier with Robust Gain Using Closed-Loop Control
- C-12-67 Digital Substrate Noise Canceling Method using Active Guard Ring
- Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability
- Autonomous di/dt Control of Power Supply for Margin Aware Operation(Electronic Circuits)
- Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
- Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs(Papers Selected from AP-ASIC 2004)
- On-Chip di/dt Detector Circuit(Microelectronic Test Structures)
- Stub vs. Capacitor for Power Supply Noise Reduction(Electronic Circuits)
- A Low Power and High Throughput Self Synchronous FPGA Using 65nm CMOS with Throughput Optimization by Pipeline Alignment
- On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
- Cascaded Time Difference Amplifier with Differential Logic Delay Cell
- All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
- 1.0ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells
- On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction