Asada K | Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo

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概要

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著作論文

Time Difference Amplifier with Robust Gain Using Closed-Loop Control
C-12-67 Digital Substrate Noise Canceling Method using Active Guard Ring
Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability
Autonomous di/dt Control of Power Supply for Margin Aware Operation(Electronic Circuits)
Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs(Papers Selected from AP-ASIC 2004)
On-Chip di/dt Detector Circuit(Microelectronic Test Structures)
Stub vs. Capacitor for Power Supply Noise Reduction(Electronic Circuits)
Noise Immunity Investigation of Low Power Design Schemes(Electronic Circuits)
On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
C-12-18 On-chip Detector for Non-Periodic High-Swing Noise Sensing
A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells(Computer Components)
A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits(Integrated Electronics)
A Logic-Cell-Embedded PLA (LCPLA) : An Area-Efficient Dual-Rail Array Logic Architecture(Integrated Electronics)
Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
A-3-7 A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells
A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers
A Structural Approach for Transistor Circuit Synthesis(Circuit Synthesis,VLSI Design and CAD Algorithms)
Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells(Circuit Synthesis, VLSI Design and CAD Algorithms)
Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization(VLSI Design Technology and CAD)
High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability(Physical Design)(VLSI Design and CAD Algorithms)
A Low Power and High Throughput Self Synchronous FPGA Using 65nm CMOS with Throughput Optimization by Pipeline Alignment
Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method
On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
Cascaded Time Difference Amplifier with Differential Logic Delay Cell
All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
1.0ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells
On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction

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