A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits(Integrated Electronics)

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概要

• 論文の詳細を見る

• This paper presents a new high-speed and area-efficient dual-rail PLA. The proposed circuit includes three schemes: 1) a divided column scheme (DCS), 2) a programmable sense-amplifier activation scheme (PSAS), and 3) an interdigitated column scheme (ICS). ln the DCS, a column circuit of a PLA is divided and each circuit operates in parallel. This enhances the performance of the PLA, and this scheme becomes more effective as input data bandwidth increases. The PSAS is used to generate an activation pulse for sense amplifiers in the PLA. In this scheme, the proposed delay generators enable to minimize a timing margin depending on process variations and operating conditions. The ICS is used to enhance the area-efficiency of the PLA, where a method of physical compaction is employed. This scheme is effective for circuits which have the regularity in logic function such as arithmetic circuits. As applications of the proposed PLA, a comparator, a priority encoder, and an incrementor for 128-bit data processing were designed. The proposed circuit design schemes achieved a 22.2% delay reduction and a 37.5% area reduction on average over the conventional high-speed and low-power PLA in a 0.13-μm CMOS technology with a supply voltage of 1.2V.

• 社団法人電子情報通信学会の論文
• 2004-06-01

著者

• Ikeda Makoto

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Ikeda Makoto

  The Vlsi Design And Education Center The University Of Tokyo

• Ikeda M

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Ikeda Makoto

  Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo

• Asada K

  Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo

• Asada K

  Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T

• Yamaoka Hiroaki

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Ikeda M

  Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo

• Asada K

  Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo

• YAMAOKA Hiroaki

  the Department of Electronics Engineering, and VLSI Design and Education Center (VDEC), The Universi

• IKEDA Makoto

  the Department of Electronics Engineering, and VLSI Design and Education Center (VDEC), The Universi

• ASADA Kunihiro

  the Department of Electronics Engineering, and VLSI Design and Education Center (VDEC), The Universi

• Asada K

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• YOSHIDA Hiroaki

  Faculty of Engineering, and VLSI Design and Education Center (VDEC), the University of Tokyo

• Asada Kunihiro

  The Department Of Electronic Engineering Faculty Of Engineering The University Of Tokyo

• Yoshida H

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Asada Kunihiro

  The Department Of Electrical Engineering And Information Systems The University Of Tokyo

• IKEDA Makoto

  the Department of Electrical Engineering and Information Systems, The University of Tokyo

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