Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme in SOI Technology
スポンサーリンク
概要
- 論文の詳細を見る
- 2006-01-26
著者
-
Ikeda Makoto
The Vlsi Design And Education Center The University Of Tokyo
-
Ikeda Makoto
Electronics Engineering Dept. Of Engineering University Of Tokyo
-
Asada Kunihiro
The Vlsi Design And Education Center The University Of Tokyo
-
Asada Kunihiro
Electronics Engineering Dept. Of Engineering University Of Tokyo
-
DIA KinHooi
The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI Design and E
-
ZHENG Ruotong
the University of Tokyo in collaboration with Oki Electric Industry Co., Ltd.
-
Dia Kinhooi
Electronics Engineering Dept. Of Engineering University Of Tokyo
-
Zheng Ruotong
Vlsi Design And Education Center (vdec) University Of Tokyo
-
Ikeda Makoto
The Vlsi Design And Education Center (vdec) The University Of Tokyo
-
Asada Kunihiro
The Vlsi Design And Education Center (vdec) The University Of Tokyo
-
ASADA Kunihiro
The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC)
関連論文
- Time Difference Amplifier with Robust Gain Using Closed-Loop Control
- Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme in SOI Technology
- Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme in SOI Technology
- C-12-67 Digital Substrate Noise Canceling Method using Active Guard Ring
- Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability
- Autonomous di/dt Control of Power Supply for Margin Aware Operation(Electronic Circuits)
- Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
- Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs(Papers Selected from AP-ASIC 2004)
- On-Chip di/dt Detector Circuit(Microelectronic Test Structures)
- Stub vs. Capacitor for Power Supply Noise Reduction(Electronic Circuits)
- Noise Immunity Investigation of Low Power Design Schemes(Electronic Circuits)
- On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
- C-12-18 On-chip Detector for Non-Periodic High-Swing Noise Sensing
- A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells(Computer Components)
- A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits(Integrated Electronics)
- A Logic-Cell-Embedded PLA (LCPLA) : An Area-Efficient Dual-Rail Array Logic Architecture(Integrated Electronics)
- Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
- Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
- A-3-7 A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells
- A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers
- A Structural Approach for Transistor Circuit Synthesis(Circuit Synthesis,VLSI Design and CAD Algorithms)
- Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells(Circuit Synthesis, VLSI Design and CAD Algorithms)
- Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization(VLSI Design Technology and CAD)
- High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability(Physical Design)(VLSI Design and CAD Algorithms)
- A Low Power and High Throughput Self Synchronous FPGA Using 65nm CMOS with Throughput Optimization by Pipeline Alignment
- Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method
- On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
- Cascaded Time Difference Amplifier with Differential Logic Delay Cell
- All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
- 1.0ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells
- On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction