A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers
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概要
- 論文の詳細を見る
In this paper, a high-speed PLA based on dynamic array logic circuits with latch sense amplifiers is presented. The present circuit consists of logic cell arrays, dual-rail bit-lines, latch sense amplifiers, and control blocks. By using a charge sharing scheme and latch sense amplifiers, voltage swings of the bit-lines are reduced compared to the conventional circuits, thus a high-speed and low-power operation is achieved. The present array logic configuration can realize any logic function expressed in the sum-of-products form by using PLA structure. As an application of the proposed PLA, a 32-bit binary comparator is designed and implemented in a 0.6-μm double-poly triple-metal CMOS process. Results of HSPICE simulation show a better performance compared to the conventional circuits. Functional testing using electron beam probing shows that the present circuit operates correctly.
- 社団法人電子情報通信学会の論文
- 2001-09-01
著者
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Ikeda Makoto
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
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Ikeda Makoto
The Vlsi Design And Education Center The University Of Tokyo
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Ikeda M
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
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Ikeda Makoto
Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo
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Asada K
Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo
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Asada K
Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T
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Yamaoka Hiroaki
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
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Ikeda M
Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo
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Asada K
Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo
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YAMAOKA Hiroaki
The Faculty of Engineering, and VLSI Design and Education Center(VDEC), the University of Tokyo
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IKEDA Makoto
The Faculty of Engineering, and VLSI Design and Education Center(VDEC), the University of Tokyo
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ASADA Kunihiro
The Faculty of Engineering, and VLSI Design and Education Center(VDEC), the University of Tokyo
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Asada K
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
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YOSHIDA Hiroaki
Faculty of Engineering, and VLSI Design and Education Center (VDEC), the University of Tokyo
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Yoshida H
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
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Asada Kunihiro
The Faculty Of Electrical Engineering And Information Systems The University Of Tokyo
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Ikeda Makoto
The Faculty Of Electrical Engineering And Information Systems The University Of Tokyo
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