A Proposal of High Speed and Low Power Data Transmission Method for VLSIs by Reduced-Swing Signal (Special Section on VLSI Design and CAD Algorithms)
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概要
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This paper presents a reduced swing signal data transmission method for the bus architectures in VLSIs, which consists of small size bus drivers of inverters, dual rail transmission lines, termination resistors and sense amplifiers for regenerating signal swing. The optimum value of signal swing and driving capacity of sense amplifier are given as functions of transmission line capacitance based on a criterion of area × delay^2 for guideline. Using results of analysis, we propose a self-controlled data transmission module for the optimum reduced swing signal. Applying the method to a 32bit bus architecture, it is shown that total area, cycle time and total power consumption are 66,070[μm^2], 0.90[ns], 32.2[mW], respectively, while those are 284,000[μm^2], 1.12[ns], 173.4[mW], respectively, in the conventional chained buffer module. The proposed method is less noisy than the conventional chained buffer method.
- 社団法人電子情報通信学会の論文
- 1993-10-25
著者
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IKEDA Makoto
The Faculty of Engineering, and VLSI Design and Education Center(VDEC), the University of Tokyo
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ASADA Kunihiro
The Faculty of Engineering, and VLSI Design and Education Center(VDEC), the University of Tokyo
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Asada Kunihiro
The Faculty Of Engineering The University Of Tokyo
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Asada Kunihiro
The Faculty Of Electrical Engineering And Information Systems The University Of Tokyo
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Ikeda Makoto
The Faculty Of Electrical Engineering And Information Systems The University Of Tokyo
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Ikeda Makoto
The Faculty Of Engineering The University Of Tokyo
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- A Proposal of High Speed and Low Power Data Transmission Method for VLSIs by Reduced-Swing Signal (Special Section on VLSI Design and CAD Algorithms)
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