A Synchronous Completion Prediction Adder (SCPA)
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概要
- 論文の詳細を見る
In this paper, a novel completion prediction adder is proposed. The basic concept is to predict the completion of an adder by investigating the inputs and generate completion signal for synchronization according to the completion prediction signal. This scheme greatly enhances the performance of an adder in both aspects of delay and hardware cost. Furthermore, the relative performance enhancement compared with representative synchronous adders increases as the word length of an adder becomes longer. For example, the delay-hardware product of SCPA for a 64-bit adder is 45.1% and 42.7% of those of binary carry look-ahead adder (BCLA) and binary tree carry look-ahead adder (BTCLA), respectively.
- 社団法人電子情報通信学会の論文
- 1997-03-25
著者
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Asada Kunihiro
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
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Asada Kunihiro
Department Of Electronic Engineering School Of Engineering The University Of Tokyo:vlsi Design And E
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Asada K
Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo
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Asada Kunihiro
Department Of Electrical And Electronic Engineering Tokyo University
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Asada K
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
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LEE Jeehan
Department of Electronic Engineering, the University of Tokyo
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Lee J
Gyeongin National Univ. Education Inchon Kor
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