Test Structure for Characterizing Capacitance Matrix of Multi-Layer Interconnects in VLSI (Special Issue on Microelectronic Test Structures)
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概要
- 論文の詳細を見る
A compact new test structure using shift register circuits for extracting components of the capacitance matrix of the multi-layer interconnections has been proposed. An extraction method of the capacitance matrix is also presented. As a result of fabrication, capacitance values obtained by measurement are in good agreement with the numerical calculation. We also showed an estimation method of the measurement errors.
- 社団法人電子情報通信学会の論文
- 1999-04-25
著者
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Asada Kunihiro
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
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ITO Hiroshi
Faculty of Engineering, Yamanashi University
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Asada Kunihiro
Faculty Of Engineering The Univ. Of Tokyo (vdec Univ. Of Tokyo)
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MIDO Tetsuhisa
Faculty of Engineering, The Univ. of Tokyo (VDEC, Univ. of Tokyo)
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Mido Tetsuhisa
Faculty Of Engineering The Univ. Of Tokyo (vdec Univ. Of Tokyo)
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Ito Hiroshi
Faculty of Computer Science & Technology, Kyushu Institute of Technology
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