Asada K | Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo
スポンサーリンク
概要
- 同名の論文著者
- Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyoの論文著者
関連著者
-
Asada K
Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo
-
Ikeda Makoto
The Vlsi Design And Education Center The University Of Tokyo
-
Ikeda Makoto
Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo
-
Asada K
Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo
-
Asada K
Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T
-
Ikeda M
Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo
-
Ikeda Makoto
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
-
Nakura Toru
Univ. Tokyo Tokyo Jpn
-
Asada K
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
-
Ikeda M
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
-
Asada Kunihiro
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
-
Asada Kunihiro
Department Of Electronic Engineering School Of Engineering The University Of Tokyo:vlsi Design And E
-
Asada Kunihiro
Department Of Electrical And Electronic Engineering Tokyo University
-
Ikeda Makoto
Department Of Agricultural Chemistry Tohoku University:(present)section Of Phytochemical Research Ei
-
Yamaoka Hiroaki
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
-
Asada Kunihiro
Vlsi Design And Education Center (vdec) The University Of Tokyo
-
YOSHIDA Hiroaki
Faculty of Engineering, and VLSI Design and Education Center (VDEC), the University of Tokyo
-
Ikeda Makoto
Vlsi Design And Education Center (vdec) The University Of Tokyo
-
Yoshida H
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
-
Nakura Toru
Vlsi Design And Education Center (vdec) The University Of Tokyo
-
IKEDA Makoto
VLSI Design and Education Center (VDEC), The University of Tokyo
-
ASADA Kunihiro
VLSI Design and Education Center (VDEC), The University of Tokyo
-
Iizuka Tetsuya
Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T
-
Mandai Shingo
Dept. Of Electronic Engineering The University Of Tokyo
-
YAMAOKA Hiroaki
Department of Electonics Engineering, Graduate School of Engineering, The University of Tokyo
-
Oike Yusuke
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
-
Asada Kunihiro
The Vlsi Design And Education Center The University Of Tokyo
-
OIKE Yusuke
Faculty of Engineering, and VLSI Design and Education Center (VDEC), the University of Tokyo
-
Ekinciel Ulkuhan
Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo
-
NAKURA Toru
VLSI Design and Education Center (VDEC), The University of Tokyo
-
Ikeda Makoto
Dept. of Electrical Engineering and Information Systems
-
Asada Kunihiro
Dept. of Electrical Engineering and Information Systems
-
Nakura Toru
Dept. Of Electronic Engineering The Univ. Of Tokyo
-
飯塚 剛
愛媛大学理学部
-
Abbas Mohamed
The Dept. Of Electronic Engineering The University Of Tokyo
-
MANDAI Shingo
Faculty of Engineering, and VLSI Design and Education Center (VDEC), The University of Tokyo
-
Iizuka Tetsuya
Department Of Electronic Engineering Faculty Of Engineering University Of Tokyo:(present Address) Re
-
Ikeda Makoto
Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T
-
Iizuka Tetsuya
Vlsi Design And Education Center (vdec) The University Of Tokyo
-
Ikeda Makoto
The Vlsi Design And Education Center (vdec) The University Of Tokyo
-
Asada Kunihiro
The Vlsi Design And Education Center (vdec) The University Of Tokyo
-
ASADA Kunihiro
The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC)
-
IIZUKA Tetsuya
Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo
-
ABBAS Mohamed
Dept. of Electronic Engineering, The University of Tokyo
-
Yoshida Hiroaki
Department of Cardiology, Himeji Cardiovascular Center
-
EKINCIEL Ulkuhan
Department of Electonics Engineering, Graduate School of Engineering, The University of Tokyo
-
Ekiniciel Ulkuhan
Department of Electronic Engineering, The University of Tokyo
-
IKEDA Makoto
The Faculty of Engineering, and VLSI Design and Education Center(VDEC), the University of Tokyo
-
Yoshida Hiroaki
Department Of Cardiology Himeji Cardiovascular Center
-
Asada Kunihiro
The Faculty Of Electrical Engineering And Information Systems The University Of Tokyo
-
Ikeda Makoto
The Faculty Of Electrical Engineering And Information Systems The University Of Tokyo
-
Yoshida Hiroaki
Department Of Applied Chemistry Graduate School Of Engineering Osaka University
-
Yoshida Hiroaki
Department Of Aeronautics And Astronautics Graduate School Of Engineering Kyoto University
-
IIZUKA Tetsuya
VLSI Design and Education Center (VDEC), The University of Tokyo
-
Kim Jinmyoung
Dept. Of Electrical Engineering And Information Systems The University Of Tokyo
-
Takata Hidehiro
Design Platform Dev. Div. Renesas Electronics Corp.
-
Ishibashi Koichiro
Design Platform Dev. Div. Renesas Electronics Corp.
-
Ekiniciel Ulkuhan
Department of Electonics Engineering, Graduate School of Engineering, The University of Tokyo
-
MANDAI Shingo
Dept. of Electronic Engineering, The University of Tokyo
-
Nakura Toru
The Dept. Of Electronic Engineering The Univ. Of Tokyo
-
Lan Dang
Dept. Of Engineering University Of Tokyo
-
NAKURA Toru
Faculty of Engineering, and VLSI Design and Education Center (VDEC), The University of Tokyo
-
NAKURA Toru
Department of Electronic Engineering, The University of Tokyo
-
YAMAOKA Hiroaki
the Department of Electronics Engineering, and VLSI Design and Education Center (VDEC), The Universi
-
IKEDA Makoto
the Department of Electronics Engineering, and VLSI Design and Education Center (VDEC), The Universi
-
ASADA Kunihiro
the Department of Electronics Engineering, and VLSI Design and Education Center (VDEC), The Universi
-
YAMAOKA Hiroaki
The Faculty of Engineering, and VLSI Design and Education Center(VDEC), the University of Tokyo
-
ASADA Kunihiro
The Faculty of Engineering, and VLSI Design and Education Center(VDEC), the University of Tokyo
-
OIKE Yusuke
Department of Electronics Engineering, University of Tokyo
-
LEE Jeehan
Department of Electronic Engineering, the University of Tokyo
-
Lee J
Gyeongin National Univ. Education Inchon Kor
-
Asada Kunihiro
The Department Of Electronic Engineering Faculty Of Engineering The University Of Tokyo
-
STEFAN DEVLIN
Dept. of Electrical Engineering and Information Systems, The University of Tokyo
-
Stefan Devlin
Dept. Of Electrical Engineering And Information Systems The University Of Tokyo
-
Yoshida Hiroaki
Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo
-
MANDAI Shingo
the Faculty of Electrical Engineering and Information Systems, The University of Tokyo
-
MOMMA Taihei
the Faculty of Electronic Engineering, The University of Tokyo
-
Mandai Shingo
The Faculty Of Electrical Engineering And Information Systems The University Of Tokyo
-
Momma Taihei
The Faculty Of Electronic Engineering The University Of Tokyo
-
Ishibashi Koichiro
Design Platform Development Division Renesas Electronics Corporation
-
KIM Jinmyoung
Dept. of Electrical Engineering and Information Systems, The University of Tokyo
-
TAKATA Hidehiro
Design Platform Development Division, Renesas Electronics Corporation
-
JEONG Jaehyun
Department of Electrical Engineering and Information Systems, The University of Tokyo
-
Jeong Jaehyun
Department Of Electrical Engineering And Information Systems The University Of Tokyo
-
Takata Hidehiro
Design Platform Development Division Renesas Electronics Corporation
-
Nakura Toru
The Vlsi Design And Education Center (vdec) The University Of Tokyo
-
Asada Kunihiro
The Department Of Electrical Engineering And Information Systems The University Of Tokyo
-
KIM Jinmyoung
the Dept. of Electrical Engineering and Information Systems, The University of Tokyo
-
Mandai Shingo
Dept. of Electrical Engineering and Information Systems
-
NAKURA Toru
Department of Electrical Engineering and Information Systems, The University of Tokyo
-
IKEDA Makoto
the Department of Electrical Engineering and Information Systems, The University of Tokyo
-
NAKURA Toru
the Department of Electrical Engineering and Information Systems, The University of Tokyo
著作論文
- Time Difference Amplifier with Robust Gain Using Closed-Loop Control
- C-12-67 Digital Substrate Noise Canceling Method using Active Guard Ring
- Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability
- Autonomous di/dt Control of Power Supply for Margin Aware Operation(Electronic Circuits)
- Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
- Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs(Papers Selected from AP-ASIC 2004)
- On-Chip di/dt Detector Circuit(Microelectronic Test Structures)
- Stub vs. Capacitor for Power Supply Noise Reduction(Electronic Circuits)
- Noise Immunity Investigation of Low Power Design Schemes(Electronic Circuits)
- On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
- C-12-18 On-chip Detector for Non-Periodic High-Swing Noise Sensing
- A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells(Computer Components)
- A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits(Integrated Electronics)
- A Logic-Cell-Embedded PLA (LCPLA) : An Area-Efficient Dual-Rail Array Logic Architecture(Integrated Electronics)
- Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
- Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
- A-3-7 A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells
- A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers
- A Structural Approach for Transistor Circuit Synthesis(Circuit Synthesis,VLSI Design and CAD Algorithms)
- Pixel-Level Color Demodulation Image Sensor for Support of Image Recognition(Electronic Circuits)
- Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories(New System Paradigms for Integrated Electronics)
- A Row-Parallel Position Detector for High-Speed 3-D Camera Based on Light-Section Method(Electronic Circuits)
- High-Sensitivity and Wide-Dynamic-Range Position Sensor Using Logarithmic-Response and Correlation Circuit
- Wide Dynamic Range Photo Detector for Smart Position Sensor Using Log-Response and Correlation Circuit
- A Synchronous Completion Prediction Adder (SCPA)
- Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells(Circuit Synthesis, VLSI Design and CAD Algorithms)
- Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization(VLSI Design Technology and CAD)
- High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability(Physical Design)(VLSI Design and CAD Algorithms)
- A Low Power and High Throughput Self Synchronous FPGA Using 65nm CMOS with Throughput Optimization by Pipeline Alignment
- Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method
- On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
- Cascaded Time Difference Amplifier with Differential Logic Delay Cell
- All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
- 1.0ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells
- On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction