Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells

スポンサーリンク

概要

• 論文の詳細を見る

• The problem of designing VLSI systems is becoming very complex. This complexity can be partially simplified by using PLAs, because of its simplicity, regularity, flexibility, programmability, and predictability. In this paper we propose a module generator, which uses a design constraint to achieve a flexible transistor sizing by a logic cell generation part. And generated logic cells can be easily adapted to layout generator. Almost all of these logic cells have 2-input. 2-input logic cells are implemented in place of conventional AND/OR planes. By using the 2-input logic cells, some classes of logic function can be implemented in a smaller circuit area. Also this module generator has a design rule interface part. With design rule interface part module generator acquires flexibility to process technologies, and module generator becomes adaptable to new process technologies.

• 社団法人電子情報通信学会の論文
• 2003-02-27

著者

• Ikeda Makoto

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Ikeda Makoto

  The Vlsi Design And Education Center The University Of Tokyo

• Ikeda M

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Ikeda Makoto

  Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo

• Ikeda Makoto

  Department Of Agricultural Chemistry Tohoku University:(present)section Of Phytochemical Research Ei

• Asada K

  Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo

• Asada K

  Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T

• Asada Kunihiro

  Department Of Electronic Engineering School Of Engineering The University Of Tokyo:vlsi Design And E

• Yamaoka Hiroaki

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Ikeda M

  Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo

• Asada K

  Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo

• Asada Kunihiro

  Department Of Electrical And Electronic Engineering Tokyo University

• YAMAOKA Hiroaki

  Department of Electonics Engineering, Graduate School of Engineering, The University of Tokyo

• Ekiniciel Ulkuhan

  Department of Electronic Engineering, The University of Tokyo

• Asada K

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• YOSHIDA Hiroaki

  Faculty of Engineering, and VLSI Design and Education Center (VDEC), the University of Tokyo

• Yoshida H

  Faculty Of Engineering And Vlsi Design And Education Center (vdec) The University Of Tokyo

• Ekinciel Ulkuhan

  Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo

• Ekiniciel Ulkuhan

  Department of Electonics Engineering, Graduate School of Engineering, The University of Tokyo

関連論文

• Time Difference Amplifier with Robust Gain Using Closed-Loop Control
• Data Bypassing Register File for Low Power Microprocessor
• Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme in SOI Technology
• C-12-67 Digital Substrate Noise Canceling Method using Active Guard Ring
• Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability
• Autonomous di/dt Control of Power Supply for Margin Aware Operation(Electronic Circuits)
• Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
• Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs(Papers Selected from AP-ASIC 2004)
• On-Chip di/dt Detector Circuit(Microelectronic Test Structures)
• Stub vs. Capacitor for Power Supply Noise Reduction(Electronic Circuits)
• Noise Immunity Investigation of Low Power Design Schemes(Electronic Circuits)
• On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
• C-12-18 On-chip Detector for Non-Periodic High-Swing Noise Sensing
• A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells(Computer Components)
• A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits(Integrated Electronics)
• A Logic-Cell-Embedded PLA (LCPLA) : An Area-Efficient Dual-Rail Array Logic Architecture(Integrated Electronics)
• Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
• Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
• A-3-7 A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells
• A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers
• SiN_x:H/SiO_2 Double-Layer Passivation With Hydrogen-Radical Annealing For Solar Cells
• Device Parameter Estimation of SOI MOSFET Using One-Dimensional Numerical Simulation Considering Quantum Mechanical Effects
• A Structural Approach for Transistor Circuit Synthesis(Circuit Synthesis,VLSI Design and CAD Algorithms)
• Pixel-Level Color Demodulation Image Sensor for Support of Image Recognition(Electronic Circuits)
• Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories(New System Paradigms for Integrated Electronics)
• A Row-Parallel Position Detector for High-Speed 3-D Camera Based on Light-Section Method(Electronic Circuits)
• High-Sensitivity and Wide-Dynamic-Range Position Sensor Using Logarithmic-Response and Correlation Circuit
• Wide Dynamic Range Photo Detector for Smart Position Sensor Using Log-Response and Correlation Circuit
• An Image Scanning Method with Selective Activation of Tree Structure (Special Issue on New Concept Device and Novel Architecture LSIs)
• A Synchronous Completion Prediction Adder (SCPA)
• Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells(Circuit Synthesis, VLSI Design and CAD Algorithms)
• Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization(VLSI Design Technology and CAD)
• High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability(Physical Design)(VLSI Design and CAD Algorithms)
• Expression profiling of favorable and unfavorable neuroblastomas
• IS-012 Expression profiling of favorable and unfavorable neuroblastomas
• P-100 NERVE PRESERVING SURGERY FOR CHILDREN WITH PELVIC TUMORS
• P-91 HICKMAN-BROVIAC CATHETER-RELALTED INFECTIONS IN CHILDREN WITH MALIGNANCY
• Non-Approximate Evaluation of Macroscopic Quantum Tunneling of Charge for the Two-Junction Case at Arbitrary Temperatures and Bias Voltages
• IS-6 Surgical treatments for patent ductus venosus in children
• P-119 Pediatric hepatic tumors wiith normal levels of serum alpha-fetoprotein
• Power Optimization for Data Compressors Based on a Window Detector in a 54 × 54 Bit Multiplier
• A Low Power and High Throughput Self Synchronous FPGA Using 65nm CMOS with Throughput Optimization by Pipeline Alignment
• A Possible Manipulation of a Biological Cell by a Laser Beam Focused through Optical Fiber
• Experimental Analysis of Optical Trapping System Using Tapered Hemispherically Lensed Optical Fiber
• Thiamine requirement of two different cultured cell lines of soybean
• Habituation in suspension-cultured soybean cells to thiamine and its precursors
• The thiamine requirement for callus formation from soybean hypocotyl
• Thiamine requirements of various plant cells in suspension culture
• Fabrication of Step-Edge Junctions on the Concave or Convex Side of YBa_2Cu_3O_ Film
• Heterogeneous subgroups in human neuroblastoma for clinically relevant risk stratification
• Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method
• Sjogren syndrome associated with multiple myeloma of the lgA _k-type
• Design of High-Speed High-Density Parallel Adders and Multipliers Using Regenerative Pass-Transistor Logic
• A Quantum Algorithm for Searching Web Communities
• Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors
• Effect of Boron on Solid Phase Epitaxy of Ge on Si(111) Surface
• A-3-12 A MONTE-CARLO ANALYSIS OF STATIC CMOS AND DUAL-RAIL PLA FOR SUB-100NM PARAMETER VARIATIONS
• Case of a 23-Year-Old Woman with Serous Surface Papilloma of Borderline Malignancy of the Left Ovary and Mucinous Cystadenoma of the Right Ovary
• Evaluation of genes identified by microarray analysis in favorable neuroblastoma
• On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
• Cascaded Time Difference Amplifier with Differential Logic Delay Cell
• All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
• 1.0ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells
• A 580fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18µm CMOS Technology
• On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction
• Thermodynamical Calculation and Experimental Confirmation of the Density of Hole Traps in SiO_2 Films
• Cascade Model for Reduction of Field-Effect Mobility of Electrons in Lightly Doped Channel of Submicron Gate Si Thin-Film Field-Effect Transistors
• Two Cases of Refractory Wegeners Granulomatosis Successfully Treated with Rituximab
• Crystallization Mechanism of Poly(l-lactic acid) under DC External Field
• C-2-15 Direct Burst Pulse Generator for Sub-millimeter Wave Integrated on 65-nm CMOS
• Study of cationic surfactant ion selective poly(vinyl chloride) membrane electrode containing dibenzo-18-crown-6.
• A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing

もっと見る 閉じる

スポンサーリンク