Design of High-Speed High-Density Parallel Adders and Multipliers Using Regenerative Pass-Transistor Logic

スポンサーリンク

概要

• 論文の詳細を見る

• Regenerative Pass-transistor Logic (RPL), a modular dual-rail circuit technique for high speed logic design that gives reasonably low power consumption, was discussed in previous work [1]. RPL combines advantages of both the compact size of CPL and the full voltage-swing of DPL, and gives reasonably high performance concerning both speed and power consumption. In this paper, the application and design technique of RPL on larger logic circuits and systems are reported. Parallel adders and Booth multipliers with different sizes and structures are used as examples to evaluate the functionality of the RPL gates and full adder. In addition, there is less signal skew in RPL circuits than in conventional CPL circuits when an arrangement of single-rail to dual-rail signal conversion is performed. And, RPL is found to be useful in design of high speed and high density parallel adders and multipliers.

• 社団法人電子情報通信学会の論文
• 1997-03-25

著者

• Asada K

  Department Of Electronic Engineering Faculty Of Engineering University Of Tokyo

• Asada Kunihiro

  Department Of Electrical And Electronic Engineering Tokyo University

• CHEUNG Tsz-Shing

  Department of Electronic Engineering, Faculty of Engineering, University of Tokyo

• Cheung Tsz-shing

  Department Of Electronic Engineering Faculty Of Engineering University Of Tokyo:fujitsu Laboratories

関連論文

• A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells(Computer Components)
• A Logic-Cell-Embedded PLA (LCPLA) : An Area-Efficient Dual-Rail Array Logic Architecture(Integrated Electronics)
• Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
• Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
• A-3-7 A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells
• Wide Dynamic Range Photo Detector for Smart Position Sensor Using Log-Response and Correlation Circuit
• A Synchronous Completion Prediction Adder (SCPA)
• Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells(Circuit Synthesis, VLSI Design and CAD Algorithms)
• Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization(VLSI Design Technology and CAD)
• High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability(Physical Design)(VLSI Design and CAD Algorithms)
• Non-Approximate Evaluation of Macroscopic Quantum Tunneling of Charge for the Two-Junction Case at Arbitrary Temperatures and Bias Voltages
• Power Optimization for Data Compressors Based on a Window Detector in a 54 × 54 Bit Multiplier
• Fabrication of Step-Edge Junctions on the Concave or Convex Side of YBa_2Cu_3O_ Film
• Design of High-Speed High-Density Parallel Adders and Multipliers Using Regenerative Pass-Transistor Logic
• A-3-12 A MONTE-CARLO ANALYSIS OF STATIC CMOS AND DUAL-RAIL PLA FOR SUB-100NM PARAMETER VARIATIONS
• A 580fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18µm CMOS Technology
• Thermodynamical Calculation and Experimental Confirmation of the Density of Hole Traps in SiO_2 Films
• Cascade Model for Reduction of Field-Effect Mobility of Electrons in Lightly Doped Channel of Submicron Gate Si Thin-Film Field-Effect Transistors
• C-2-15 Direct Burst Pulse Generator for Sub-millimeter Wave Integrated on 65-nm CMOS

もっと見る 閉じる

スポンサーリンク