Power Optimization for Data Compressors Based on a Window Detector in a 54 × 54 Bit Multiplier
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概要
- 論文の詳細を見る
Currently, a typical 54 × 54 bit multiplier is composed of a parallel structured architecture with the encoder block to implement the Modified Booth's algorithm, a block to implement the data compression, and a 108-bit Carry Look-Ahead (CLA) adder. The key idea in the present paper is a power optimization for the data compressors based on a Window Detector. The role of the Window Detector is detecting the input data, activating a selected operation unit, choosing the optimized output data, and driving the next stae. It can reduce the power consumption drastically because only one selected operation unit (a Window) is activated. The power consumption of the proposed data compressors is reduced by about 33%, compared with that of the conventional multiplier; while the propagation delay is nearly same as that of the conventional one. Furthermore, the power consumption dependent on the input data transition is shown for both the static CMOS logic and the nMOS pass transistor logic.
- 社団法人電子情報通信学会の論文
- 1997-07-25
著者
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Asada Kunihiro
Department Of Electronic Engineering School Of Engineering The University Of Tokyo:vlsi Design And E
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Asada Kunihiro
Department Of Electronic Engineering The University Of Tokyo
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Asada Kunihiro
Department Of Electrical And Electronic Engineering Tokyo University
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SONG Minkyu
Department of Semiconductor Science, Dongguk University
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Song Minkyu
Department Of Semiconductor Science Dongguk University
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