Fabrication of Step-Edge Junctions on the Concave or Convex Side of YBa_2Cu_3O_<7-x> Film
スポンサーリンク
概要
- 論文の詳細を見る
Step-edge junctions using YBa_2Cu_3O_<7-x>, (YBCO) film are fabricated with two types of patterns. One has the bridge structure only at the concave side of the edge and the other, only at the convex side. The steps are fabricated by etching MgO substrates with hydrochloric acid solution, and YBCO films are deposited using rf-sputtering and subsequent annealing. It is shown from the current-voltage (I-V) characteristics of these patterns at 4.2 K that the grain boundary required for the formation of step-edge junctions tends to be built up on the convex side of the step.
- 社団法人応用物理学会の論文
- 1992-11-15
著者
-
Asada Kunihiro
Department Of Electronic Engineering School Of Engineering The University Of Tokyo:vlsi Design And E
-
SUGANO Takuo
Department of Electrical and Electronic Engineering, Toyo University
-
KATO Kei
Department of Applied Chemistry, Faculty of Engineering, Gunma University
-
Asada Kunihiro
Department Of Electrical And Electronic Engineering Tokyo University
-
Kato K
Asahikawa Medical School Asahikawa Jpn
-
Sugiura M
Department Of Electronic Engineering The University Of Tokyo
-
Kato Kei
Department Of Applied Chemistry Faculty Of Engineering Gunma University
-
SUGIURA Masayuki
Department of Electronic Engineering, The University of Tokyo
-
Sugano Takuo
Department Of Electronic Engineering The University Of Tokyo
関連論文
- Beating of the Shubnikov-de Haas Oscillations in GaAs/AlGaAs Quantum-Dot Arrays
- Selective Si-Si Bond Cleavage of Decaisopropylbicyclo[2.2.0]hexasilane with Hydrobromic Acid and Hydrochloric Acid
- A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells(Computer Components)
- A Logic-Cell-Embedded PLA (LCPLA) : An Area-Efficient Dual-Rail Array Logic Architecture(Integrated Electronics)
- Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
- Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
- A-3-7 A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells
- Advantages of the Asymmetric Tunnel Barrier for High-Density Integration of Single Electron Devices ( Quantum Dot Structures)
- Single Electron Device with Asymmetric Tunnel Barriers
- A Perspective on Next-Generation Silicon Devices
- Wide Dynamic Range Photo Detector for Smart Position Sensor Using Log-Response and Correlation Circuit
- A Synchronous Completion Prediction Adder (SCPA)
- Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells(Circuit Synthesis, VLSI Design and CAD Algorithms)
- Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization(VLSI Design Technology and CAD)
- High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability(Physical Design)(VLSI Design and CAD Algorithms)
- Non-Approximate Evaluation of Macroscopic Quantum Tunneling of Charge for the Two-Junction Case at Arbitrary Temperatures and Bias Voltages
- Power Optimization for Data Compressors Based on a Window Detector in a 54 × 54 Bit Multiplier
- Electron Mobility in In_Ga_xAs Epitaxial Layer
- Calculations of Energy Levels of Oxygen and Silicon Vacancies at the Si-SiO_2 Interface
- Fabrication of Josephson Weak Links Using Electron Beam Lithography and Ion-Etching, and Proposal of a New Single Flux Quantum Logic : C-2: JOSEPHSON DEVICES
- Interface Analysis of Al_2O_3/InP Structure Prepared by Molecular Beam Deposition
- Fabrication of Step-Edge Junctions on the Concave or Convex Side of YBa_2Cu_3O_ Film
- Magnetic and Electrical Properties of Vacuum-Deposited CdCr_2Se_4 Thin Film
- Design of High-Speed High-Density Parallel Adders and Multipliers Using Regenerative Pass-Transistor Logic
- Studies on Chemically Etched Silicon, Gallium Arsenide, and Gallium Phosphide Surfaces by Auger Electron Spectroscopy
- Ordered Structure and Ion Migration in Silicon Dioxide Films
- Hall Mobility of Electrons in Silicon Surface Inversion Layers
- Galvanomagnetic Effects in Silicon Surface Inversion Layers
- Mobility of Magnetic Domain Wall of Strip Domain in Garnet Crystal : Computer Simulation and Measurement : B-2: BUBBLE DEVICES (II)
- Optical Properties of Vacuum-Deposited CdCr_2Se_4 Thin Film
- Effects of PAs_xN_y Deposition Conditions and the Cd Concentration in the Substrates on the Characteristics of In_Ga_As Metal-Insulator-Semiconductor Field Effect Transistors : Special Section : Solid State Devices and Materials 2 : III-V Comp
- Deep Level Transient Spectroscopy of Bulk Traps and Interface States in Si MOS Diodes
- Epitaxial Growth of SiC Film on Silicon Substrate and Its Crystal Structure
- Fabrication of Bi_2Sr_2CaCu_2O_x High T_c Superconducting Film with H_2O Assisted Metalorganic Chemical Vapor Deposition
- A-3-12 A MONTE-CARLO ANALYSIS OF STATIC CMOS AND DUAL-RAIL PLA FOR SUB-100NM PARAMETER VARIATIONS
- Vapor Deposition of Silicon Nitride Film on Silicon and Properties of MNS Diodes
- Physical and Technological Limits in Size of Semiconductor Devices : E-2: PHYSICAL AND TECHNOLOGICAL LIMITS OF HIGH-DENSITY INTERGRATION
- Forward Characteristics of Si Schottky Diodes
- Plasma-Oxidized Tunnel Barrier of Nb/Nb Josephson Junctions with Copper Interlayer
- Scattering of Electrons by Potential Clusters in Ternary Alloy Semiconductor
- Proposal for Criterion on Deformation of III-V Ternary Alloy Crystal Lattice
- Chemical Deposition of Mo on Si
- Magnetic Modulation of Critical Current in MB DC-SQUID
- Fabrication of Si-Mo-Si Three Layer Structure and Its Current Transfer Characteristics
- Anodization of Silicon in RF Induced Oxygen Plasma : A-2: MOS DEVICES/BASIC ASPECTS
- Hot Electron-Phonon Interaction in Metals
- Defect-Free Reactive Ion Etching of Silicon by SiF_4/Cl_2 Plasma
- A 580fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18µm CMOS Technology
- Thermodynamical Calculation and Experimental Confirmation of the Density of Hole Traps in SiO_2 Films
- Beating of the Shubnikov-de Haas Oscillations in GaAs/AlGaAs Quantum-Dot Arrays
- Electrokinetic Evaluation of Individual Exosomes by On-Chip Microcapillary Electrophoresis with Laser Dark-Field Microscopy
- Cascade Model for Reduction of Field-Effect Mobility of Electrons in Lightly Doped Channel of Submicron Gate Si Thin-Film Field-Effect Transistors
- C-2-15 Direct Burst Pulse Generator for Sub-millimeter Wave Integrated on 65-nm CMOS
- Advantages of the Asymmetric Tunnel Barrier for High-Density Integration of Single Electron Devices
- Neuroprotective Therapy Using Granulocyte Colony-Stimulating Factor for Patients With Worsening Symptoms of Thoracic Myelopathy : A Multicenter Prospective Controlled Trial
- Electrokinetic Evaluation of Individual Exosomes by On-Chip Microcapillary Electrophoresis with Laser Dark-Field Microscopy