A 580fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18µm CMOS Technology
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概要
- 論文の詳細を見る
This paper proposes a sub-ps resolution TDC utilizing a differential pulse-shrinking buffer ring. This scheme uses two differentially-operated pulse-shrinking inverters and the TDC resolution is finely controlled by the transistor size ratio between them. The proposed TDC realizes 9bit, 580fs resolution in a 0.18µm CMOS technology with 0.04mm2 area, and achieves DNL and INL of +0.8/-0.8LSB and +4.3/-4.0LSB, respectively, without linearity calibration. A power dissipation at 1.5MS/s ranges from 10.8 to 12.6mW depending on the input time intervals.
著者
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Asada Kunihiro
Department Of Electrical And Electronic Engineering Tokyo University
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Chiba Yutaka
Thine Electronics Inc.
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Miura Satoshi
Thine Electronics Inc.
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Kubo Shunichi
Thine Electronics Inc.
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Yamamoto Ryota
Thine Electronics Inc.
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IIZUKA Tetsuya
Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo
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IIZUKA Tetsuya
Department of Electrical Engineering and Information Systems, The University of Tokyo
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ASADA Kunihiro
Department of Electrical Engineering and Information Systems, The University of Tokyo
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- A 580fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18µm CMOS Technology
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