Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme in SOI Technology

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概要

• 論文の詳細を見る

• This paper presents a new footless dual-rail domino circuit that efficiently combines a footless dynamic circuit technique with a robust self-timed precharge scheme for high performance VLSI design. Along with these, the proposed circuit achieves a whole footless dual-rail domino circuit with the use of the proposed separator. A 20-stage NAND chain with fan-out 8 is implemented in 0.15-μm SOI CMOS technology for performance evaluation. Measurement results reveal that the proposed circuit achieves 2.57, 1.72 and 1.12 times speed improvement over the circuit implemented with CPL, the conventional static CMOS and the conventional dynamic DCVSL, respectively.

• 社団法人電子情報通信学会の論文
• 2006-01-19

著者

• Ikeda Makoto

  Electronics Engineering Dept. Of Engineering University Of Tokyo

• Asada Kunihiro

  Electronics Engineering Dept. Of Engineering University Of Tokyo

• DIA KinHooi

  Electronics Engineering, Dept. of Engineering, University of Tokyo

• ZHENG Ruotong

  VLSI Design and Education Center (VDEC), University of Tokyo

• Dia Kinhooi

  Electronics Engineering Dept. Of Engineering University Of Tokyo

• Zheng Ruotong

  Vlsi Design And Education Center (vdec) University Of Tokyo

• Asada Kunihiro

  Electrical Engineering and Information Systems, University of Tokyo:VLSI Design and Education Center (VDEC), University of Tokyo

• ASADA Kunihiro

  Electronics Engineering, Dept. of Engineering, University of Tokyo:VLSI Design and Education Center (VDEC), University of Tokyo

関連論文

• Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme in SOI Technology
• Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme in SOI Technology

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