Design of Low Power Digital VLSI Circuits Based on a Novel Pass-Transistor Logic

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概要

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• In this paper, a novel pass-transistor logic with an efficient level restoration circuit, named Power Saved Pass-transistor Logic (PSPL), is proposed. It is shown how, through the use of regenerative feedback with pMOS switches, we reduce the power consumption and propagation delay compared to eonventional pass-transistor logic. To demonstrate the performance of PSPL, a 54×54-bit multiplier is designed. For speed and power optimization, the multiplier uses high compression-rate compressors without Booth Encoding, and a 108-bit conditional sum adder with separated carry generation block. The measured multiplication time was 13.5 ns in a 0.6 μm single-poly triple metal 3.3 V CMOS process. Furthermore, a sequential circuit of a low power 7-bit serial counter is designed and fabricated in a 0.6μm single-poly triple-metal 3.3 V CMOS process. The measured operating speed was 250 MHz.

• 社団法人電子情報通信学会の論文
• 1998-11-25

著者

• ASADA Kunihiro

  the Department of Electronics Engineering, and VLSI Design and Education Center (VDEC), The Universi

• Asada Kunihiro

  The Department Of Electronic Engineering Faculty Of Engineering The University Of Tokyo

• Asada Kunihiro

  The Department Of Electronic Engineering University Of Tokyo

• SONG Minkyu

  the Department of Semiconductor Science, Dongguk University

• Song Minkyu

  The Department Of Semiconductor Science Dongguk University

• Asada Kunihiro

  The Department Of Electrical Engineering And Information Systems The University Of Tokyo

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