Influence of the Relaxation Current in Ba_xSr_lt(1-x)gtTiO_3 Thin Film Capacitors on DRAM Operation
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概要
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This paper describes influence of the relaxation current in Ba_xSr_lt(1-x)gtTiO_3 (BST) thin films on dynamic random access memory (DRAM) operation. The relaxation current is a transient content of dielectric leakage currents. In BST thin films (expected to be a cell capacitor dielectric in 256 Mb DRAM and beyond), the relaxation current often displays the power law behavior I (t)〜t^lt-1gt. This leads to the singularity near the time zero. When one attempts to evaluate precisely the influence of this leakage on DRAM operation, the behavior should be estimated on a time-dependent bias. However, such a singular behavior makes analysis based on a linear response difficult. In this analysis, we start by assuming that the behavior of the relaxation current can be modeled as a linear equivalent circuit. We also assume that the relaxation current follows the power law, I(t)〜t^lt-1gt for 1 ns lt t gt 1 s. Then, the voltage drop across the capacitor due to the relaxation current is expressed by a integral equation. The singularity is isolated after the integral equation is transformed. All the parameters in the transformed integral equation are related to finite measured quantities. The transformed equation is solved by iteration, and the problem of the logarithmic divergence is consistently solved. The BST films fabricated in our experiment show an average voltage drop of 7 to 10% during the refresh period of 1 s. This will be a concern for 256 Mb DRAMs and beyond.
- 社団法人電子情報通信学会の論文
- 1997-07-25
著者
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Fukuda Y
Texas Instruments Tsukuba Res. And Dev. Center Ltd. Ibaraki Jpn
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Fukuda Y
Department Of Physics Faculty Of Science Kobe University
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Fukuda Yukio
Texas Instruments Tukuba Research & Development Center Limited
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Kakimi A
Texas Instruments Tsukuba Res. And Dev. Center Ltd. Ibaraki Jpn
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Okuno Yasutoshi
Lsi Manufacturing Technology Unit Wafer Process Engineering Development Division Renesas Technology
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AOKI Katsuhiro
Texas Instruments Tsukuba Research and Development Center, Limited
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Okuno Y
Lsi Manufacturing Technology Unit Wafer Process Engineering Development Division Renesas Technology
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Numata K
The Authors Are With Memory Research & Development Center Texas Instruments Inc.
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Aoki Katsuhiro
Texas Instruments Tsukuba Research & Development Center Limited
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Nishimura Akitoshi
The Authors Are With Memory Research & Development Center Texas Instruments Inc.
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NUMATA Ken
Texas Instruments Japan, ULSI Technology Center
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OKUNO Yasutoshi
Texas Instruments Japan, ULSI Technology Center
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NISHIMURA Akitoshi
Texas Instruments Japan, ULSI Technology Center
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奥野 泰利
日本テキサスインスツルメンツ(株)、ulsi技術開発センター
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奥野 泰利
松下電器産業(株)
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Fukuda Yukio
Texas Instruments Tsukuba Research & Development Center Limited
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Okuno Yasutoshi
ULSI Process Technology Development Center, Semiconductor Company, Matsushita Electronics Corp., 19, Nishikujo-kasuga cho, Minami-ku, Kyoto 601-8413, Japan
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