Hot-Carrier-Induced Degradation on 0.1 μm Partially Depleted Silicon-On-Insulator Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor

スポンサーリンク

概要

• 論文の詳細を見る
• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2003-04-30

著者

• FANG Yean-Kuen

  VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, Nat

• Fang Yean-kuen

  Vlsi Technology Laboratory Department Of Electrical Engineering National Cheng Kuang University

• Fang Yean-kuen

  Vlsi Technology Lab. Institute Of Microelectronics Ee Department National Cheng Kung University No.

• YEH Wen-Kuan

  Department of Electrical Engineering, National University of Kaohsiung

• Yeh Wen-kuan

  Department Of Electrical Engineering National University Of Kaohsiung

• Yeh W‐k

  National Univ. Of Kaohsiung Kaohsiung Twn

• Yang Fu-liang

  Taiwan Semiconductor Manufacturing Company Exploratory Device Dept. Device Engineering Division Scie

• Yang Fu-liang

  Taiwan Semiconductor Manufacturing Company

• Wang Wen-han

  Vlsi Technology Laboratory Institute Of Microelectronics Department Of Electrical Engineering Nation

• Fang Yean-kuen

  Vlsi Technology Laboratory Institute Of Microelectronics Department Of Electrical Engineering Nation

• Wang Wen-han

  Vlsi Technology Laboratory Institute Of Microelectronics Department Of Electrical Engineering Nation

関連論文

• Mechanism of Chemical Mechanical Planarization Induced Edge Corrosion of Copper Line for Cu/Low-k SiOC Interconnects
• Efficient Improvement on Device Performance for sub-90nm CMOSFETs
• An Efficient Mobility Enhancement Engineering on 65nm FUSI CMOSFETs using a Second CESL Process
• Systematic Analysis and Modeling of On-Chip Spiral Inductors for CMOS RFIC Application
• Mobility Modulation Technology Impact on Device Performance and Reliability for sub-90nm SOI CMOSFETs
• The Impact of Body-Potential on Hot-Carrier-Induced Device Degradation for 90nm Partially-Depleted SOI nMOSFETs
• Width Effect on Hot-Carrier-Induced Degradation for 90nm Partially Depleted SOI CMOSFETs
• Width Effect on Hot-Carrier-induced Degradation for 90nm Partially Depleted SOI CMOSFET
• The Impact of Pad Test-Fixture for De-embedding on Radio-Frequency MOSFETs
• Low-Frequency Noise in Partially Depleted SOI MOSFETs Operating from Linear Region to Saturation Region at Various Temperatures
• Effects of hot carriers on DC and RF performances of deep submicron PMOSFET for low-power and high frequency applications
• Electrical and Optical Characteristics of an a-Si:H/c-Si Heterojunction Switch
• The Growth and Characterization of Silicon/Silicon Carbide Heteroepitaxial Films on Silicon Substrates by Rapid Thermal Chemical Vapor Deposition
• A Comparison of Behaviors between Hydrogenated/Unhydrogenated Polysilicon Thin Film Transistors under Electric Stress
• Improvement on Fluorine Effect under High Field Stress in Tungsten-Polycide Gated Metal-Oxide-Semiconductor Field-Effect Transistor with Oxynitride and/or Reoxidized-Oxynitride Gate Dielectric
• An Efficient Improvement for Barrier Effect of W-filled Contact
• An Efficient Improvement for Barrier Effect of W-Filled Contact
• Epitaxial Growth and Electrical Characteristics of β-SiC on Si by Low-Pressure Rapid Thermal Chemical Vapor Deposition
• Hot-Carrier-Induced Degradation on 0.1 μm Partially Depleted Silicon-On-Insulator Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor
• Effects of Tungsten Polycide Process and Post-Polyoxidation Rapid Thermal Process on Electrical Characteristics of Thin Polysilicon Oxide
• Anomalous Current-Voltage Characteristics and Threshold Voltage Shift in Implanted-Polysilicon-Gated Complementary Metal-Oxide-Semiconductor Field-Effect Transistors with/without Titanium-Polycide Technology
• A Novel Amorphous Silicon Double Barrier Homojunction Device with Negative Resistance
• Novel Amorphous-Crystallime Silicon Heterojunction Switching Devices with Bidirectional Switching Characteristics
• Amorphous Silicon Double-Injection Device with Gate-Controllable N-Type Negative Resistance
• A Novel Amorphous Silicon Doping Superlattice Device with a Controllable Gate
• High Current Density in Amorphous Silicon/Siliconcarbide Double-Barrier Resonant Tunneling Device on Aluminum/Silicon Substrate
• New Observations on Hot-Carrier Degradation in 0.1 μm Silicon-on-Insulator n-Type Metal Oxide Semiconductor Field Effect Transistors : Semiconductors
• Efficient Suppression of Substrate Noise Coupling in Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor Technology
• Strain Efficiency Enhancement with Stress Intermedium Engineering (SIE) for Sub-65nm CMOS Scaling
• The Reliability Characteristics of Wafer-Level Chip-Scale Package under Various Current Stressing
• Effect of STI Stress Enhanced Boron Diffusion on Leakage and Vcc min of Sub-65nm node Low-Power SRAM
• Embedded Process and Characterization Analysis of Discrete Capacitor in Organic-Base Substrate
• Impacts of Layout Dimensions and Ambient Temperatures on Silicon Based On-Chip RF Interconnects
• Effect of Etch Stop Layer Stress on Negative Bias Temperature Instability of Deep Submicron p-Type Metal–Oxide–Semiconductor Field Effect Transistors with Dual Gate Oxide
• Extra Bonus on Transistor Optimization with Stress Enhanced Notched-Gate Technology for Sub-90 nm Complementary Metal Oxide Semiconductor Field Effect Transistor
• Efficient Mobility Enhancement Engineering on 65 nm Fully Silicide Complementary Metal–Oxide–Semiconductor Field-Effect-Transistors Using Second Contect Etch Stop Layer Process
• Investigation and Modeling of Stress Interactions on 90 nm Silicon on Insulator Complementary Metal Oxide Semiconductor by Various Mobility Enhancement Approaches
• Observation of Reliability of HfZrOX Gate Dielectric Devices with Different Zr/Hf Ratios
• A study of deposition single crystal SiCN thin film on porous silicon for ultraviolet light detecting applications
• SOI Transistor/Power Scaling and Scaling-Strengthened Strain
• A Study of Relationship of Wafer Breakage vs. Wafer Edge Analysis
• Elucidating the Effects of Current Stress History on Reliability Characteristics by Dynamic Analysis
• Reliability and Characteristics of Wafer-Level Chip-Scale Packages under Current Stress
• Effects of Hot Carriers on DC and RF Performances of Deep Submicron p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Various Oxide Layer Thicknesses
• Stress Technology Impact on Device Performances and Reliability for $\langle100\rangle$ Sub-90 nm Silicon-on-Insulator Complementary Metal–Oxide–Semiconductor Field-Effect-Transistors
• Width Effect on Hot-Carrier-Induced Degradation for 90 nm Partially Depleted SOI CMOSFETs
• Hot-Carrier-Induced Degradation on 0.1 μm Partially Depleted Silicon-On-Insulator Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor
• Low-Frequency Noise in Partially Depleted SOI MOSFETs Operating from Linear Region to Saturation Region at Various Temperatures
• Investigation of the Relationship between Whole-Wafer Strength and Control of Its Edge Engineering
• β-SiC Photodiodes Prepared on Silicon Substrates by Rapid Thermal Chemical Vapor Deposition
• An Efficient Improvement for Barrier Effect of W-filled Contact
• Systematic Analysis and Modeling of On-Chip Spiral Inductors for Complementary Metal Oxide Semiconductor Radio Frequency Integrated Circuits Applications
• Improvement on Fluorine Effect under High Field Stress in Tungsten-Polycide Gated Metal-Oxide-Semiconductor Field-Effect Transistor with Oxynitride and/or Reoxidized-Oxynitride Gate Dielectric

もっと見る 閉じる

スポンサーリンク