Reliability and Characteristics of Wafer-Level Chip-Scale Packages under Current Stress

スポンサーリンク

概要

• 論文の詳細を見る

• In this work, we present a novel approach and method for elucidating the characteristics of wafer-level chip-scale packages (WLCSPs) for electromigration (EM) tests. The die in WLCSP was directly attached to the substrate via a soldered interconnect. The shrinking of the area of the die that is available for power, and the solder bump also shrinks the volume and increases the density of electrons for interconnect efficiency. The bump current density now approaches to $10^{6}$ A/cm2, at which point the EM becomes a significant reliability issue. As known, the EM failure depends on numerous factors, including the working temperature and the under bump metallization (UBM) thickness. A new interconnection geometry is adopted extensively with moderate success in overcoming larger mismatches between the displacements of components during current and temperature changes. Both environments and testing parameters for WLCSP are increasingly demanded. Although failure mechanisms are considered to have been eliminated or at least made manageable, new package technologies are again challenging its process, integrity and reliability. WLCSP technology was developed to eliminate the need for encapsulation to ensure compatibility with smart-mount technology (SMT). The package has good handing properties but is now facing serious reliability problems. In this work, we investigated the reliability of a WLCSP subjected to different accelerated current stressing conditions at a fixed ambient temperature of 125 °C. A very strong correlation exists between the mean time to failure ($\mathit{MTTF}$) of the WLCSP test vehicle and the mean current density that is carried by a solder joint. A series of current densities were applied to the WLCSP architecture; Black’s power law was employed in a failure mode simulation. Additionally, scanning electron microscopy (SEM) was adopted to determine the differences existing between high- and low-current-density failure modes.

• 2008-02-25

著者

• Yeh Wen-kuan

  Department Of Electrical Engineering National University Of Kaohsiung

• Lai Yi-shao

  Stress-reliability Lab Advanced Semiconductor Engineering Inc.

• Kung Heng-yu

  Department Of Electronic Engineering National University Of Kaohsiung

• Tsai Ming

  Department Of Computer Science And Engineering National Sun Yat-sen University

• Lai Yi-Shao

  Stress-Reliability Lab, Advanced Semiconductor Engineering, Inc., Nan-Tzu District, Kaohsiung, Taiwan 811, R.O.C.

• Chen Po-Ying

  Department of Information Engineering, I-Shou University, No. 1, Sec. 1, Syuecheng Road, Dashu Township, Kaohsiung County, Taiwan 840, R.O.C.

• Chen Po-Ying

  Department of Information Engineering, I-Shou University, Kaohsiung County, Taiwan 840, R.O.C.

• Tsai Ming

  Department of Electronic Engineering, National University of Kaohsiung, No. 700, Kaohsiung University Road, Nan-Tzu District, Kaohsiung, Taiwan 811, R.O.C.

• Kung Heng-Yu

  Department of Electronic Engineering, National University of Kaohsiung, No. 700, Kaohsiung University Road, Nan-Tzu District, Kaohsiung, Taiwan 811, R.O.C.

• Yeh Wen-Kuan

  Department of Electronic Engineering, National University of Kaohsiung, No. 700, Kaohsiung University Road, Nan-Tzu District, Kaohsiung, Taiwan 811, R.O.C.

関連論文

• Successful cord blood transplantation in a girl with monosomy 7 myelodysplastic syndrome and reduced numbers of B cells
• Efficient Improvement on Device Performance for sub-90nm CMOSFETs
• An Efficient Mobility Enhancement Engineering on 65nm FUSI CMOSFETs using a Second CESL Process
• Systematic Analysis and Modeling of On-Chip Spiral Inductors for CMOS RFIC Application
• Mobility Modulation Technology Impact on Device Performance and Reliability for sub-90nm SOI CMOSFETs
• The Impact of Body-Potential on Hot-Carrier-Induced Device Degradation for 90nm Partially-Depleted SOI nMOSFETs
• Width Effect on Hot-Carrier-induced Degradation for 90nm Partially Depleted SOI CMOSFET
• The Impact of Pad Test-Fixture for De-embedding on Radio-Frequency MOSFETs
• An Efficient Improvement for Barrier Effect of W-Filled Contact
• Hot-Carrier-Induced Degradation on 0.1 μm Partially Depleted Silicon-On-Insulator Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor
• New Observations on Hot-Carrier Degradation in 0.1 μm Silicon-on-Insulator n-Type Metal Oxide Semiconductor Field Effect Transistors : Semiconductors
• The Reliability Characteristics of Wafer-Level Chip-Scale Package under Various Current Stressing
• Embedded Process and Characterization Analysis of Discrete Capacitor in Organic-Base Substrate
• Impacts of Layout Dimensions and Ambient Temperatures on Silicon Based On-Chip RF Interconnects
• A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition(Digital Circuits and Computer Arithmetic, Recent Advances in Circuits and Systems-Part
• Efficient Mobility Enhancement Engineering on 65 nm Fully Silicide Complementary Metal–Oxide–Semiconductor Field-Effect-Transistors Using Second Contect Etch Stop Layer Process
• A Study of Relationship of Wafer Breakage vs. Wafer Edge Analysis
• Elucidating the Effects of Current Stress History on Reliability Characteristics by Dynamic Analysis
• Reliability and Characteristics of Wafer-Level Chip-Scale Packages under Current Stress
• Bursting firing of action potentials in central snail neurons elicited by d-amphetamine: role of cytoplasmic second messengers
• Stress Technology Impact on Device Performances and Reliability for $\langle100\rangle$ Sub-90 nm Silicon-on-Insulator Complementary Metal–Oxide–Semiconductor Field-Effect-Transistors
• Width Effect on Hot-Carrier-Induced Degradation for 90 nm Partially Depleted SOI CMOSFETs
• Hot-Carrier-Induced Degradation on 0.1 μm Partially Depleted Silicon-On-Insulator Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor
• Low-Frequency Noise in Partially Depleted SOI MOSFETs Operating from Linear Region to Saturation Region at Various Temperatures
• Investigation of the Relationship between Whole-Wafer Strength and Control of Its Edge Engineering
• An Efficient Improvement for Barrier Effect of W-filled Contact
• Systematic Analysis and Modeling of On-Chip Spiral Inductors for Complementary Metal Oxide Semiconductor Radio Frequency Integrated Circuits Applications
• Cytogenetic similarities between the formosan serow (Capricornis swinhoi) and the Japanese serow (Capricornis crispus).:Capricornis crispus

もっと見る 閉じる

スポンサーリンク