Investigation and Modeling of Stress Interactions on 90 nm Silicon on Insulator Complementary Metal Oxide Semiconductor by Various Mobility Enhancement Approaches
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概要
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The interactions of shallow trench isolation (STI) stress and various mobility enhancement approaches in silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) have been systematically studied. Strong interactions between STI stress and contact etch stop layer (CESL) stress on channel mobility were observed which was attributed to the amplification of CESL channel tensile stress with length of diffusion (LOD) reduction. In this work, an almost completely reversed P-channel metal oxide semiconductor field-effect transistor (PMOSFET) mobility-LOD trend in both $ \langle 110 \rangle $/(100) and $ \langle 100 \rangle $/(100) oriented SOI wafers was found, which is caused by the reversed polarity of piezoresistance coefficients. On the other hand, charge pumping leakage was enhanced by the post-gate oxide stress (CESL stress) only, and was not affected by any stress applied prior to the gate oxidation step (STI stress).
- 2006-04-30
著者
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Fang Yean-kuen
Vlsi Technology Lab. Institute Of Microelectronics Ee Department National Cheng Kung University No.
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Yeh Wen-kuan
Electrical Engineering Department National University Of Kaohsiung
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Lee Tung-hsing
Vlsi Technology Lab. Institute Of Microelectronics Ee Department National Cheng Kung University No.
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Chen Liang-Wei
Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, Hsin-Chu City, Taiwan 30007
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Lin Chien-Ting
VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan
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Hsu Che-Hua
Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, HsinChu City 300, Taiwan
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Lin Chien-Ting
VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
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Chen Ming-Hing
VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
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Chang Hui-Chen
Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, Hsin-Chu City, Taiwan 30007
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Tsai Cheng-Tzung
Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, Hsin-Chu City, Taiwan 30007
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Ma Mike
Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, Hsin-Chu City, Taiwan 30007
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Chang Hui-Chen
Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, Hsin-Chu City, Taiwan 30007
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Hsu Che-Hua
Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, Hsin-Chu City, Taiwan 30007
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Yeh Wen-Kuan
Electrical Engineering Department, National University of Kaohsiung, No. 700, Kaohsiung University Rd., Nan-Tzu Dist., Kaohsiung, Taiwan
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Lee Tung-Hsing
VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
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Ma Mike
Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, Hsin-Chu City, Taiwan 30007
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Tsai Cheng-Tzung
Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, Hsin-Chu City, Taiwan 30007
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