Extra Bonus on Transistor Optimization with Stress Enhanced Notched-Gate Technology for Sub-90 nm Complementary Metal Oxide Semiconductor Field Effect Transistor

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概要

• 論文の詳細を見る

• A simple and efficient strain engineering technique for integrating the tensile-stress contact etch stop layer (CESL) process to a notch gate has been reported in detail. The strain engineering technique utilizes slight process modifications to modulate the channel stress and implantation profile for the enhancement of performance without adding any extra process steps. Compared with the conventional vertical-gate complementary metal oxide semiconductor field effect transistor (CMOSFET) with an offset spacer, a device with a notch gate as a self-aligned offset spacer achieves an extra 7% NMOS $I_{\text{ON}}$ enhancement. The enhancement comes from the larger channel stress induced by the tensile-stress CESL on the notch gate, and is confirmed by technology computer aided design (TCAD) simulation. Moreover, fewer interface defects ($D_{\text{it}}$) and parasitic capacitances were obtained for the notch-gate samples.

• 2007-04-30

著者

• Fang Yean-kuen

  Vlsi Technology Lab. Institute Of Microelectronics Ee Department National Cheng Kung University No.

• Yeh Wen-kuan

  Electrical Engineering Department National University Of Kaohsiung

• Huang Yao-Tsung

  Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, HsinChu City 300, Taiwan

• Lin Chien-Ting

  VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan

• Lai Chieh-Ming

  VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan

• Hsu Che-Hua

  Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, HsinChu City 300, Taiwan

• Cheng Li-Wei

  Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, HsinChu City 300, Taiwan

• Ma Guang

  Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, HsinChu City 300, Taiwan

• Ma Guang

  Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, HsinChu City 300, Taiwan

• Cheng Li-Wei

  Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, HsinChu City 300, Taiwan

• Hsu Che-Hua

  Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, HsinChu City 300, Taiwan

• Hsu Che-Hua

  Central R&D Division, United Microelectronics Corporation (UMC), No. 3, Li-Hsin Rd. II, Hsin-Chu City, Taiwan 30007

• Yeh Wen-Kuan

  Electrical Engineering Department, National University of Kaohsiung, No. 700, Kaohsiung University Rd., Nan-Tzu Dist., Kaohsiung 811, Taiwan

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