Effect of Etch Stop Layer Stress on Negative Bias Temperature Instability of Deep Submicron p-Type Metal–Oxide–Semiconductor Field Effect Transistors with Dual Gate Oxide
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概要
- 論文の詳細を見る
Negative bias temperature instability (NBTI) in a dual-gate-oxide complementary metal–oxide–semiconductor (CMOS) process induces threshold voltage ($V_{\text{t}}$) shift and has become a crucial challenge in designing advanced analog or mixed-signal circuits. In this paper, the impact of the stress from a contact etch stop layer (CESL) on the NBTI of dual-gate-oxide input/output (I/O) p-type MOS field effect transistors (P-MOSFETs) is investigated in detail. Experimental results show that applying tensile stress can suppress NBTI-induced $V_{\text{t}}$ shift more significantly than applying compressive stress, thus becoming a simple and effective method of relieving NBTI.
- 2008-04-25
著者
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Fang Yean-kuen
Vlsi Technology Lab. Institute Of Microelectronics Ee Department National Cheng Kung University No.
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Chiang Yen-ting
Vlsi Technology Laboratory Institute Of Microelectronics Department Of Electrical Engineering Nation
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Shen Tsong
United Microelectronics Corporation (umc) Specialty Technology Division
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Ko Joe
United Microelectronics Corporation (umc) Specialty Technology Division
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Sheu Yau
United Microelectronics Corporation (umc) Specialty Technology Division
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Liao Wen
United Microelectronics Corporation (umc) Specialty Technology Division
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Lee Tung-hsing
Vlsi Technology Lab. Institute Of Microelectronics Ee Department National Cheng Kung University No.
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Lin Chien-Ting
VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan
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Chen Ming-Shing
VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan
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Ko Joe
United Microelectronics Corporation (UMC), Specialty Technology Division, No. 3, Li-Hsin Rd. II, Hsinchu 300, Taiwan
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Chiang Yen-Ting
VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan
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Liao Wen
United Microelectronics Corporation (UMC), Specialty Technology Division, No. 3, Li-Hsin Rd. II, Hsinchu 300, Taiwan
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Shen Tsong
United Microelectronics Corporation (UMC), Specialty Technology Division, No. 3, Li-Hsin Rd. II, Hsinchu 300, Taiwan
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Fang Yean-Kuen
VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan
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Lee Tung-Hsing
VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan
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Sheu Yau
United Microelectronics Corporation (UMC), Specialty Technology Division, No. 3, Li-Hsin Rd. II, Hsinchu 300, Taiwan
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