Investigation of the Relationship between Whole-Wafer Strength and Control of Its Edge Engineering
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概要
- 論文の詳細を見る
Silicon wafer breakage has become a major concern for all semiconductor fabrication lines because it is brittle, and thus high stresses are easily induced in its manufacture. The production cost of devices significantly increases even for a breakage loss of a few percent if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant. In this investigation, we develop a brand new approach to reducing breakage by using a charge-coupled device (CCD) to capture the cross-section image of the wafer at its edge; the data measured at the edge can be used to determine overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength, and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in the wafer bulk before failure. We also describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unidentified causes. Our analysis gives the optimal front size ($B_{1}$), edge widths ($A_{1},A_{2}$), and bevel angle ($\theta$) for the edge profiles of wafers to prevent wafer breakage. Briefly, when a suitable material and suitable process control approaches are utilized, silicon wafer breakage can be prevented. This is the first investigation providing evidence that whole-wafer strength is an important issue. We present a physical model to explain why wafer fracture has become an increasingly serious problem as the diameter of wafers has increased. The control of wafer edge geometry has been demonstrated to be an effective means of protecting wafers with large diameters against breakage. This model reveals that the breakage rate of wafers can be reduced by controlling the uniformity of the differences between the front size and the rear edge widths during the wafer manufacturing process.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2009-12-25
著者
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Tsai Ming-hsing
Department Of Electronics Engineering National Chiao Tung University And National Nano Device Labora
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Yeh Wen-kuan
Department Of Electrical Engineering National University Of Kaohsiung
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Chen Po-Ying
Department of Information Engineering, I-Shou University, No. 1, Sec. 1, Syuecheng Road, Dashu Township, Kaohsiung County, Taiwan 840, R.O.C.
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Chen Po-Ying
Department of Information Engineering, I-Shou University, Kaohsiung County, Taiwan 840, R.O.C.
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Chang YuKon
Department of Information Engineering, I-Shou University, Kaohsiung County, Taiwan 840, R.O.C.
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Chang Yukon
Department of Information Engineering, I-Shou University, No. 1, Sec. 1, Syuecheng Road, Dashu Township, Kaohsiung County, Taiwan 840, R.O.C.
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Jing Ming-Haw
Department of Information Engineering, I-Shou University, No. 1, Sec. 1, Syuecheng Road, Dashu Township, Kaohsiung County, Taiwan 840, R.O.C.
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Yeh Wen-Kuan
Department of Electronic Engineering, National University of Kaohsiung, No. 700, Kaohsiung University Road, NanTzu District, Kaohsiung, Taiwan 811, R.O.C.
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Tsai Ming-Hsing
Department of Electronic Engineering, National University of Kaohsiung, No. 700, Kaohsiung University Road, NanTzu District, Kaohsiung, Taiwan 811, R.O.C.
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