Stress Technology Impact on Device Performances and Reliability for $\langle100\rangle$ Sub-90 nm Silicon-on-Insulator Complementary Metal–Oxide–Semiconductor Field-Effect-Transistors

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概要

• 論文の詳細を見る

• In this work, we investigated the thickness effect of a high-stress gate capping layer (GC layer) on $\langle100\rangle$ 90 nm partially-depleted silicon-on-insulator complementary metal–oxide–semiconductor field-effect transistor (PD-SOI CMOSFETs). Additionally, we inspected the hot-carrier reliability on body-contacted (BC) SOI devices with various thicknesses of the GC layer (1100 and 700 Å) and a conventional SiN layer (CN layer). For nMOSFETs, devices with an 1100 Å GC layer possess worse characteristics and hot-carrier degradations than devices with a 700 Å GC layer in terms of excess high tensile stress. For pMOSFETs, the GC layer only slightly affects device performance, but seriously affects hot-carrier-induced device degradation. Therefore, the thickness of this high-stress GC layer should be optimized to improve the device performance.

• 2006-04-30

著者

• Lai Chieh-ming

  Institute Of Microelectronics National Cheng Kung University

• Fang Yean-kuen

  Institute Of Microelectronics National Cheng Kung University

• Yeh Wen-kuan

  Department Of Electrical Engineering National University Of Kaohsiung

• Yeh Wen-Kuan

  Department of Electrical Engineering, National University of Kaohsiung, No. 700, Kaohsiung University Road., Nan-Tzu Dist., Kaohsiung 811, Taiwan, R.O.C.

• Fang Yean-Kuen

  Institute of Microelectronics, National Cheng Kung University, No. 1 University Road, Tainan 70101, Taiwan, R.O.C.

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