Stress Technology Impact on Device Performances and Reliability for <100> Sub-90nm Silicon-on-Insulator Complementary Metal-Oxide-Semiconductor Field-Effect-Transistors (Special Issue: Solid State Devices & Materials)

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概要

• 論文の詳細を見る
• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文

著者

• Lai Chieh-ming

  Institute Of Microelectronics National Cheng Kung University

関連論文

• Efficient Improvement on Device Performance for sub-90nm CMOSFETs
• An Efficient Mobility Enhancement Engineering on 65nm FUSI CMOSFETs using a Second CESL Process
• Stress Technology Impact on Device Performances and Reliability for Sub-90nm Silicon-on-Insulator Complementary Metal-Oxide-Semiconductor Field-Effect-Transistors (Special Issue: Solid State Devices & Materials)
• Systematic Analysis and Modeling of On-Chip Spiral Inductors for CMOS RFIC Application
• Mobility Modulation Technology Impact on Device Performance and Reliability for sub-90nm SOI CMOSFETs
• The Impact of Body-Potential on Hot-Carrier-Induced Device Degradation for 90nm Partially-Depleted SOI nMOSFETs
• Width Effect on Hot-Carrier-Induced Degradation for 90nm Partially Depleted SOI CMOSFETs
• Width Effect on Hot-Carrier-induced Degradation for 90nm Partially Depleted SOI CMOSFET
• The Impact of Pad Test-Fixture for De-embedding on Radio-Frequency MOSFETs
• Extra bonus on transistor optimization with stress enhanced notched-gate technology for sub-90nm complementary metal oxide semiconductor field effect transistor (Special issue: Solid state devices and materials)
• Efficient mobility enhancement engineering on 65nm fully silicide complementary metal-oxide-semiconductor field-effect-transistors using second contect etch stop layer process (Special issue: Solid state devices and materials)
• Investigation and Modeling of Stress Interactions on 90nm Silicon on Insulator Complementary Metal Oxide Semiconductor by Various Mobility Enhancement Approaches (Special Issue: Solid State Devices & Materials)
• Efficient Mobility Enhancement Engineering on 65 nm Fully Silicide Complementary Metal–Oxide–Semiconductor Field-Effect-Transistors Using Second Contect Etch Stop Layer Process
• Stress Technology Impact on Device Performances and Reliability for $\langle100\rangle$ Sub-90 nm Silicon-on-Insulator Complementary Metal–Oxide–Semiconductor Field-Effect-Transistors
• Width Effect on Hot-Carrier-Induced Degradation for 90 nm Partially Depleted SOI CMOSFETs

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